Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-12396181-B2
Application number	US-202118024286-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Sep 22, 2020
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel portion, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel portion and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, so that power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are formed to be stacked; therefore, the length of a wiring between the circuits can be shortened, and a low-power consumption operation and a high-speed operation can be performed.

First claim

The invention claimed is:

1. An imaging device comprising a plurality of pixel blocks,
wherein the plurality of pixel blocks comprise a first layer and a second layer,
wherein the first layer comprises a region overlapped with the second layer,
wherein each of the plurality of pixel blocks comprises:
a plurality of pixel circuits and a plurality of first memory circuits in the first layer; and
a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer,

wherein the plurality of pixel circuits and the plurality of first memory circuits each comprise a transistor including a metal oxide comprising In in a channel formation region,
wherein each of the plurality of first memory circuits is configured to retain a weight coefficient to be supplied to the plurality of product-sum operation circuits,
wherein each of the plurality of first memory circuits comprises a memory cell, and
wherein the memory cell comprises a capacitor including a ferroelectric layer.

2. An imaging device comprising a plurality of pixel blocks,
wherein the plurality of pixel blocks comprise a first layer and a second layer,
wherein the first layer is positioned over the second layer,
wherein each of the plurality of pixel blocks comprises:
a plurality of pixel circuits and a plurality of first memory circuits in the first layer; and
a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer,

wherein each of the plurality of pixel circuits and each of the plurality of first memory circuits are overlapped with each other,
wherein the plurality of pixel circuits and the plurality of first memory circuits each comprise a transistor including a metal oxide comprising In in a channel formation region,
wherein each of the plurality of first memory circuits is configured to retain a weight coefficient to be supplied to the plurality of product-sum operation circuits,
wherein each of the plurality of first memory circuits comprises a memory cell, and
wherein the memory cell comprises a capacitor including a ferroelectric layer.

3. The imaging device according to claim 1 ,
wherein the plurality of product-sum operation circuits, the plurality of first binarization circuits, and the plurality of second binarization circuits each comprise a transistor including silicon in a channel formation region.

4. The imaging device according to claim 1 ,
wherein a number of the plurality of pixel circuits is the same as a number of the plurality of first binarization circuits.

5. The imaging device according to claim 1 ,
wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits,
wherein each of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits, and
wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits.

6. The imaging device according to claim 1 ,
wherein a number of the plurality of first binarization circuits is larger than a number of the plurality of second binarization circuits.

7. The imaging device according to claim 1 ,
wherein a number of the plurality of product-sum operation circuits is the same as a number of the plurality of second binarization circuits.

8. The imaging device according to claim 1 ,
wherein a driver circuit of the plurality of pixel circuits and a driver circuit of the plurality of first memory circuits are provided in the second layer.

9. The imaging device according to claim 1 , further comprising a second memory circuit,
wherein an input terminal of the second memory circuit is electrically connected to the plurality of second binarization circuits, and
wherein an output terminal of the second memory circuit is electrically connected to the plurality of product-sum operation circuits.

10. The imaging device according to claim 9 , further comprising a third memory circuit and a third binarization circuit,
wherein the third memory circuit is electrically connected to the plurality of product-sum operation circuits with the third binarization circuit therebetween.

11. The imaging device according to claim 10 ,
wherein the second memory circuit, the third memory circuit, and the third binarization circuit are provided in the second layer.

12. The imaging device according to claim 1 ,
wherein the metal oxide further comprises Zn, and M, M being one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.

13. An electronic device comprising the imaging device according to claim 1 , and a display device.

14. The imaging device according to claim 2 ,
wherein the plurality of product-sum operation circuits, the plurality of first binarization circuits, and the plurality of second binarization circuits each comprise a transistor including silicon in a channel formation region.

15. The imaging device according to claim 2 ,
wherein a number of the plurality of pixel circuits is the same as a number of the plurality of first binarization circuits.

16. The imaging device according to claim 2 ,
wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits,
wherein each of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits, and
wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits.

17. The imaging device according to claim 2 ,
wherein a number of the plurality of first binarization circuits is larger than a number of the plurality of second binarization circuits.

18. The imaging device according to claim 2 ,
wherein a number of the plurality of product-sum operation circuits is the same as a number of the plurality of second binarization circuits.

19. The imaging device according to claim 2 ,
wherein a driver circuit of the plurality of pixel circuits and a driver circuit of the plurality of first memory circuits are provided in the second layer.

20. The imaging device according to claim 2 , further comprising a second memory circuit,
wherein an input terminal of the second memory circuit is electrically connected to the plurality of second binarization circuits, and
wherein an output terminal of the second memory circuit is electrically connected to the plurality of product-sum operation circuits.

21. The imaging device according to claim 20 , further comprising a third memory circuit and a third binarization circuit,
wherein the third memory circuit is electrically connected to the plurality of product-sum operation circuits with the third binarization circuit therebetween.

22. The imaging device according to claim 21 ,
wherein the second memory circuit, the third memory circuit, and the third binarization circuit are provided in the second layer.

23. The imaging device according to claim 2 ,
wherein the metal oxide further comprises Zn, and M, M being one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.

24. An electronic device comprising the imaging device according to claim 2 , and a display device.

Assignees

• Semiconductor Energy Lab

Inventors

• Negoro Yusuke
• Shishido Hideaki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10F39/8023 Primary

  Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title

• H10F39/182

  Colour image sensors · CPC title

• H10K39/601

  Assemblies of multiple devices comprising at least one organic radiation-sensitive element · CPC title