Imaging device and electronic device using three dimentional (3D) integration

US10020336B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10020336-B2
Application numberUS-201615383327-A
CountryUS
Kind codeB2
Filing dateDec 19, 2016
Priority dateDec 28, 2015
Publication dateJul 10, 2018
Grant dateJul 10, 2018

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

First claim

Opening claim text (preview).

What is claimed is: 1. An imaging device comprising: a first layer comprising a photoelectric conversion element, a third insulating layer, and a fifth metal layer; a second layer comprising a first transistor comprising an oxide semiconductor in an active layer, a fourth insulating layer, and a sixth metal layer; and a third layer comprising a second transistor comprising silicon in an active layer or an active region, wherein the second layer is provided between the first layer and the third layer, wherein the fifth metal layer and the sixth metal layer are formed using metal elements of a same main component, wherein the fifth metal layer comprises a region embedded in the third insulating layer and a region bonded to the sixth metal layer, wherein the sixth metal layer comprises a region embedded in the fourth insulating layer, wherein the third insulating layer comprises a region bonded to the fourth insulating layer, wherein the photoelectric conversion element is electrically connected to the fifth metal layer, and wherein the first transistor and the second transistor are electrically connected to the fifth metal layer and the first transistor, respectively. 2. The imaging device according to claim 1 , wherein the metal element is Cu, Al, W, or Au. 3. The imaging device according to claim 1 , wherein the oxide semiconductor comprises In, Zn, and M (M is Al, Ga, Y, or Sn). 4. A module comprising a lens and the imaging device according to claim 1 . 5. An electronic device comprising a display device and the imaging device according to claim 1 . 6. An imaging device comprising: a third layer comprising a second transistor comprising silicon in an active layer or an active region; a second layer comprising a first transistor comprising an oxide semiconductor in an active layer, a fourth insulating layer, and a sixth metal layer, the second layer being over the third layer; and a first layer comprising a photoelectric conversion element, a third insulating layer, and a fifth metal layer, the first layer being over the second layer, wherein the fifth metal layer and the sixth metal layer are formed using metal elements of a same main component, wherein the fifth metal layer is in contact with the sixth metal layer, wherein the third insulating layer is in contact with the fourth insulating layer, and wherein the photoelectric conversion element is electrically connected to the fifth metal layer. 7. The imaging device according to claim 6 , wherein the metal element is Cu, Al, W, or Au. 8. The imaging device according to claim 6 , wherein the oxide semiconductor comprises In, Zn, and M (M is Al, Ga, Y, or Sn). 9. A module comprising a lens and the imaging device according to claim 6 . 10. An electronic device comprising a display device and the imaging device according to claim 6 .

Assignees

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Classifications

  • characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

  • characterised by the direct bonding of electrically conductive pads · CPC title

  • Dispositions of bond pads · CPC title

  • between multiple chips · CPC title

  • Electricity · mapped topic

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What does patent US10020336B2 cover?
An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second struc…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L27/14634. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).