DRAM computation circuit and method

Patent metadata

Field	Value
Publication number	US-12394469-B2
Application number	US-202418743950-A
Country	US
Kind code	B2
Filing date	Jun 14, 2024
Priority date	Jul 29, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

First claim

What is claimed is:

1. A memory circuit comprising:
a boundary layer;
a first circuit positioned on a first side of the boundary layer and comprising a dynamic random-access memory (DRAM) array, wherein the DRAM array comprises a plurality of DRAM cells;
a second circuit positioned on a second side of the boundary layer opposite the first side and comprising a computation circuit, wherein the computation circuit comprises a sense amplifier circuit; and
a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit, wherein each bit line of the plurality of bit lines comprises a via structure positioned in the boundary layer,
wherein the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

2. The memory circuit of claim 1 , wherein
the sense amplifier circuit comprises a plurality of sense amplifiers, and
each sense amplifier of the plurality of sense amplifiers comprises an input terminal coupled to a bit line of the plurality of bit lines.

3. The memory circuit of claim 2 , wherein
the input terminal of each sense amplifier of the plurality of sense amplifiers is coupled to more than one bit line of the plurality of bit lines.

4. The memory circuit of claim 2 , wherein
each sense amplifier of the plurality of sense amplifiers comprises an output terminal coupled to a corresponding NOR gate.

5. The memory circuit of claim 2 , wherein
the computation circuit further comprises an analog-to-digital-converter (ADC), and
each sense amplifier of the plurality of sense amplifiers comprises an output terminal coupled to the ADC.

6. The memory circuit of claim 1 , wherein
the plurality of bit lines comprises the via structures positioned in the boundary layer in a single row.

7. The memory circuit of claim 1 , wherein
the plurality of bit lines comprises the via structures positioned in the boundary layer in multiple rows.

8. The memory circuit of claim 1 , wherein
the first circuit further comprises a control circuit,
the memory circuit further comprises a control line coupled between the control circuit and the sense amplifier circuit, and
the control line comprises a control line via structure positioned in the boundary layer.

9. An integrated circuit (IC) device package comprising:
a structural layer;
a first semiconductor die positioned on a first side of the structural layer and comprising a dynamic random-access memory (DRAM) array, wherein the DRAM array comprises a plurality of DRAM cells;
a second semiconductor die positioned on a second side of the structural layer opposite the first side and comprising a computation circuit, wherein the computation circuit comprises a sense amplifier circuit; and
a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit, wherein each bit line of the plurality of bit lines comprises a via structure positioned in the structural layer,
wherein the plurality of DRAM cells of the first semiconductor die positioned on the first side of the structural layer is an entirety of the DRAM cells of the IC device package coupled to the sense amplifier circuit.

10. The IC device package of claim 9 , wherein
the sense amplifier circuit comprises a plurality of digital sense amplifiers, and
each digital sense amplifier of the plurality of digital sense amplifiers comprises:
an input terminal coupled to a bit line of the plurality of bit lines; and
an output terminal coupled to a corresponding NOR gate.

11. The IC device package of claim 9 , wherein
the computation circuit further comprises an analog-to-digital-converter (ADC),
the sense amplifier circuit comprises a plurality of analog sense amplifiers, and
each analog sense amplifier of the plurality of analog sense amplifiers comprises:
an input terminal coupled to a bit line of the plurality of bit lines; and
an output terminal coupled to the ADC.

12. The IC device package of claim 9 , wherein
the via structures of the plurality of bit lines are arranged in a single row in the structural layer.

13. The IC device package of claim 9 , wherein
the via structures of the plurality of bit lines are arranged in multiple rows in the structural layer.

14. The IC device package of claim 9 , wherein
the first circuit further comprises a control circuit,
the memory circuit further comprises a plurality of control lines coupled between the control circuit and the sense amplifier circuit, and
each control line of the plurality of control lines comprises a control line via structure positioned in the structural layer.

15. A method of operating a memory circuit, the method comprising:
generating a plurality of bit line signals from a plurality of weight data elements stored in a plurality of dynamic random-access memory (DRAM) cells positioned on a first side of a boundary layer;
propagating the plurality of bit line signals along via structures positioned in the boundary layer;
receiving the plurality of bit line signals at a sense amplifier circuit of a computation circuit positioned on a second side of the boundary layer; and
using the computation circuit to generate an output signal by performing one or more operations based on an input signal and sense amplifier signals generated by the sense amplifier circuit,
wherein the plurality of DRAM cells positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

16. The method of claim 15 , wherein
the performing the one or more operations based on the input signal and sense amplifier signals comprises receiving the input signal and the sense amplifier signals at input terminals of a plurality of NOR gates.

17. The method of claim 15 , wherein
the performing the one or more operations based on the input signal and sense amplifier signals comprises receiving the input signal and the sense amplifier signals at an analog-to-digital-converter (ADC).

18. The method of claim 15 , wherein
the performing the one or more operations comprises receiving the input signal comprising data elements having a number of bits equal to a number of bits of the weight data elements stored in the plurality of DRAM cells.

19. The method of claim 15 , wherein
the performing the one or more operations based on the input signal and sense amplifier signals comprises performing a summation function, a scaling function, or a rectified linear unit function.

20. The method of claim 15 , further comprising:
using a clock signal propagated along a control line via structure positioned in the boundary layer to synchronize the generating the plurality of bit line signals and the using the computation circuit to generate the output signal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chieh
• Huang Chia-En
• Liu Yi-Ching
• Cheng Wen-Chang
• Wang Yih

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title