Sense amplification device in memory

Patent metadata

Field	Value
Publication number	US-2022020421-A1
Application number	US-202016928010-A
Country	US
Kind code	A1
Filing date	Jul 14, 2020
Priority date	Jul 14, 2020
Publication date	Jan 20, 2022
Grant date	—

Abstract

A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

First claim

1 . A sense amplification device, comprising:
a first sense amplifier, having an input terminal coupled to a first bit line and amplifying data signals of the first bit line; a second sense amplifier, having an input terminal coupled to a second bit line and amplifying data signals of the second bit line; and a third sense amplifier, having a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier, wherein the first sense amplifier comprises:
a first transistor, having a first terminal coupled to a first reference voltage, wherein a second terminal of the first transistor is coupled to the output terminal of the first sense amplifier, and a control terminal of the first transistor is controlled by a first control signal; and
a second transistor, having a first terminal coupled to the input terminal of the first sense amplifier, wherein a second terminal of the second transistor is coupled to the second terminal of the first transistor, and a control terminal of the second transistor is controlled by a second control signal,
wherein the first transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor and the second transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.

2 . The sense amplification device according to claim 1 , wherein each of the first sense amplifier and the second sense amplifier is a non-differential signal amplifier, and the third sense amplifier is a differential signal amplifier.

3 - 4 . (canceled)

5 . The sense amplification device according to claim 1 , wherein
during a bit line pre-charge period before a word line enable period, the first control signal turns on the first transistor and the second control signal drives the second transistor to pre-charge the first bit line; during an initialization period of the word line enable period, the first control signal turns on the first transistor and the second control signal turns off the second transistor; and during a sense period of the word line enable period after the initialization period, the first control signal turns off the first transistor and the second control signal drives the second transistor to sense the first bit line.

6 . The sense amplification device according to claim 5 , wherein
during the sense period and in a case where data of the first bit line is in a first logic state, the second transistor is turned off; and during the sense period and in a case where the data of the first bit line is in a second logic state, the second transistor is turned on.

7 . The sense amplification device according to claim 1 , wherein
during a period of the second sense amplifier sensing the second bit line, the first control signal turns on the first transistor and the second control signal turns off the second transistor.

8 . The sense amplification device according to claim 1 , wherein the first sense amplifier further comprises:
a control circuit, having an input terminal coupled to the input terminal of the first sense amplifier and configured to generate the second control signal to the control terminal of the second transistor, wherein the control circuit dynamically adjusts the second control signal according to a level of the input terminal of the first sense amplifier.

9 . The sense amplification device according to claim 8 , wherein the control circuit comprises:
a third transistor, having a first terminal receiving a third control signal, wherein a second terminal of the third transistor is coupled to an output terminal of the control circuit to generate the second control signal to the control terminal of the second transistor, and a control terminal of the third transistor is controlled by a second reference voltage; and a fourth transistor, having a first terminal receiving a fourth control signal, wherein a second terminal of the fourth transistor is coupled to the second terminal of the third transistor, and a control terminal of the fourth transistor is coupled to the input terminal of the control circuit.

10 . The sense amplification device according to claim 9 , wherein the third transistor comprises a PMOS transistor and the fourth transistor comprises an NMOS transistor.

11 . The sense amplification device according to claim 1 , wherein the third sense amplifier comprises:
a fifth transistor, having a first terminal coupled to a first voltage, wherein a second terminal of the fifth transistor is coupled to the first output terminal of the third sense amplifier, and a control terminal of the fifth transistor is coupled to the second output terminal of the third sense amplifier; a sixth transistor, having a first terminal coupled to the first voltage, wherein a second terminal of the sixth transistor is coupled to the second output terminal of the third sense amplifier, and a control terminal of the sixth transistor is coupled to the first output terminal of the third sense amplifier; a seventh transistor, having a first terminal coupled to a second voltage, wherein a second terminal of the seventh transistor is coupled to the first output terminal of the third sense amplifier, and a control terminal of the seventh transistor is coupled to the second input terminal of the third sense amplifier; and a eighth transistor, having a first terminal coupled to the second voltage, wherein a second terminal of the eighth transistor is coupled to the second output terminal of the third sense amplifier, and a control terminal of the eighth transistor is coupled to the first input terminal of the third sense amplifier.

Assignees

• Winbond Electronics Corp

Inventors

• Kadowaki Takuya

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title