Two-stage read/write 3D architecture for memory devices

Patent metadata

Field	Value
Publication number	US-9851915-B2
Application number	US-201715627837-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Apr 23, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells;
a control circuit configured to perform a first read/write operation during a first time interval by writing a first data value to the first group of memory cells while concurrently reading a second data value from the second group of memory cells;
wherein the control circuit is further configured to perform a second read/write operation during a second time interval by writing a third data value to the third group of memory cells while concurrently reading a fourth data value from the fourth group of memory cells, the second time interval being after the first time interval; and
wherein the first data value and third data value are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device at a time prior to the first time interval.

2. The memory device of claim 1 :
wherein the control circuit comprises an address decoder configured to assert a first wordline coupled to respective gates of respective access transistors for the first group of memory cells and configured to concurrently assert a second wordline coupled to respective gates of respective access transistors for the second group of memory cells; and
wherein a first group of bitlines, which are coupled to respective source/drain regions of the respective access transistors for the first group of memory cells, correspond to odd bits of the N-bit input data word, and wherein a second group of bitlines, which are coupled to respective source/drain regions of the respective access transistors for the second group of memory cells, correspond to even bits of the N-bit input data word.

3. The memory device of claim 2 , further comprising:
a shared write circuit comprising a multiplexer configured to receive an odd bit and an even bit corresponding to two successive bits in the N-bit input data word from a single memory pin of the memory device, and further configured to selectively pass either the odd bit or the even bit, but not both, at a given time to the memory cell array.

4. The memory device of claim 1 , wherein the first group of memory cells and the third group of memory cells are each disposed on a first semiconductor substrate, and wherein the second group of memory cells and the fourth group of memory cells are each disposed on a second semiconductor substrate separate from the first semiconductor substrate.

5. The memory device of claim 4 , wherein the first semiconductor substrate and the second semiconductor substrate are enclosed within an integrated circuit package.

6. The memory device of claim 1 , wherein the first group of memory cells, the second group of memory cells, the third group of memory cells, and the fourth group of memory cells reside on a single substrate, and are enclosed by an integrated circuit package.

7. The memory device of claim 1 , wherein the first group of memory cells, the second group of memory cells, the third group of memory cells, and the fourth group of memory cells are made up of static random access memory (SRAM) cells.

8. The memory device of claim 1 , wherein the first group of memory cells and the third group of memory cells are included in a first memory cell array on a first tier, and wherein the second group of memory cells and the fourth group of memory cells are included in a second memory cell array on a second tier, the second tier being arranged over the first tier, or vice versa.

9. The memory device of claim 8 , wherein an electrical connection between the first tier and the second tier comprises an inter-tier via with a diameter of less than about 100 nm.

10. The memory device of claim 8 :
wherein the control circuit comprises an address decoder configured to assert a first wordline coupled to respective gates of respective access transistors for the first group of memory cells on the first tier and configured to concurrently assert a second wordline coupled to respective gates of respective access transistors for the second group of memory cells on the second tier; and
wherein a first group of bitlines, which are coupled to respective source/drain regions of the respective access transistors for the first group of memory cells on the first tier, correspond to odd bits of the N-bit input data word, and wherein a second group of bitlines, which are coupled to respective source/drain regions of the respective access transistors for the second group of memory cells on the second tier, correspond to even bits of the N-bit input data word.

11. A memory device comprising:
a memory cell array comprising a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells;
a control circuit configured to perform a first read/write operation during a first time interval by writing a first data value to the first group of memory cells while concurrently reading a second data value from the second group of memory cells;
wherein the control circuit is further configured to perform a second read/write operation during a second time interval by writing a third data value to the third group of memory cells while concurrently reading a fourth data value from the fourth group of memory cells, the second time interval being after the first time interval; and
wherein the second data value and the fourth data value are collectively made up of N-bits and collectively correspond to an N-bit output data word provided onto output pins of the memory device at a time after the second time interval.

12. The memory device of claim 11 , further comprising:
a shared read circuit comprising a de-multiplexer configured receive an odd bit and even bit corresponding to two successive bits in the N-bit output data word from the memory cell array, and further configured to selectively pass either the odd bit or the even bit, but not both, at a given time to a single output pin of the memory device.

13. The memory device of claim 11 :
wherein the control circuit comprises an address decoder configured to assert a first wordline coupled to respective gates of respective access transistors for the first group of memory cells and configured to concurrently assert a second wordline coupled to respective gates of respective access transistors for the second group of memory cells; and
wherein a first group of bitlines, which are coupled to respective source/drain regions of the respective access transistors for the first group of memory cells, correspond to odd bits of the N-bit output data word, and wherein a second group of bitlines, which are coupled to the respective source/drain regions of respective access transistors for the second group of memory cells, correspond to even bits of the N-bit output data word.

14. The memory device of claim 11 , wherein the first group of memory cells and the third group of memory cells are each disposed on a first semiconductor substrate, and wherein the second group of memory cells and the fourth group of memory cells are each disposed on a second semiconductor substrate separate from the first semiconductor substrate.

15. The memory device of claim 14 , wherein the first semiconductor substrate and the second semiconductor substrate are enclosed within an integrated circuit package.

16. The memory device of claim 11 , wherein the first group of memory cells, the second group of memory cells, the third group of memory cells, and the fo

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Kuang Ting
• Wu Ching-Wei

Classifications

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G11C2207/108

  Wide data ports · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L27/1104

  Electricity · mapped topic