DRAM computation circuit and method

Patent metadata

Field	Value
Publication number	US-12014768-B2
Application number	US-202217589729-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Jul 29, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.

First claim

What is claimed is:

1. A memory circuit comprising:
a first circuit comprising a dynamic random-access memory (DRAM) array, wherein the DRAM array comprises a plurality of bit lines;
a second circuit comprising a computation circuit, wherein the computation circuit comprises a sense amplifier circuit; and
a boundary layer positioned between the first and second circuits,
wherein
the boundary layer comprises a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit, and
the plurality of bit lines electrically connected to the sense amplifier circuit by the plurality of via structures are an entirety of the bit lines electrically connected to the sense amplifier circuit.

2. The memory circuit of claim 1 , wherein
the first circuit comprises a first semiconductor die,
the second circuit comprises a second semiconductor die, and
the plurality of via structures is positioned in one or more structural layers of an integrated circuit package comprising the first and second semiconductor dies.

3. The memory circuit of claim 1 , wherein
the first circuit comprises a first layer of a semiconductor die,
the second circuit comprises a second layer of the semiconductor die, and
the plurality of via structures is positioned in a dielectric layer of the semiconductor die.

4. The memory circuit of claim 1 , wherein
the sense amplifier circuit is configured to generate a plurality of digital signals based on a plurality of bit line signals on the plurality of bit lines, and
the computation circuit further comprises:
a plurality of NOR gates configured to generate a plurality of output signals based on the plurality of digital signals and an input signal; and
an adder tree configured to generate a summation data element based on the plurality of output signals.

5. The memory circuit of claim 1 , wherein
the sense amplifier circuit is configured to generate a plurality of analog signals based on a plurality of bit line signals on the plurality of bit lines, and
the computation circuit comprises an analog-to-digital converter configured to, based on the plurality of analog signals and an input signal, perform one or more of a summation function, a scaling function, or a rectified linear unit function.

6. The memory circuit of claim 5 , wherein the computation circuit further comprises an adder tree configured to perform at least a portion of the summation function.

7. The memory circuit of claim 1 , wherein
the DRAM array comprises a plurality of DRAM cells coupled to the plurality of bit lines, and
each DRAM cell of the plurality of DRAM cells comprises a single transistor and a single capacitor.

8. The memory circuit of claim 1 , wherein
the memory array comprises a plurality of rows,
each row of the plurality of rows comprises a plurality of memory cells coupled to the plurality of bit lines, and
the plurality of memory cells of each row of the plurality of rows is configured to store a plurality of weight data elements.

9. The memory circuit of claim 8 , wherein the memory circuit is configured to generate, sequentially by row, a plurality of signals on the plurality of bit lines based on the weight data elements.

10. A neural network circuit comprising:
a first circuit;
a second circuit;
a boundary layer positioned between the first and second circuits; and
a memory circuit comprising:
an array of dynamic random-access memory (DRAM) cells positioned in the first circuit;
a computation circuit positioned in the second circuit, wherein the computation circuit comprises a sense amplifier circuit; and
a plurality of bit lines coupled to each of the array of DRAM cells and the computation circuit,
wherein
each bit line of the plurality of bit lines comprises a via structure positioned in the boundary layer, and
the plurality of bit lines comprising the via structures positioned in the boundary layer are an entirety of the bit lines electrically connected to the sense amplifier circuit.

11. The neural network circuit of claim 10 , wherein
the sense amplifier circuit is configured to receive a plurality of signals on the plurality of bit lines, the plurality of signals being based on weight data elements stored in the array of DRAM cells, and
the computation circuit is configured to perform a matrix operation based on the plurality of signals and an input signal.

12. The neural network circuit of claim 11 , wherein
the sense amplifier circuit is configured to generate a plurality of digital signals based on the plurality of signals, and
the computation circuit further comprises:
a plurality of NOR gates configured to generate a plurality of output signals based on the plurality of digital signals and the input signal; and
an adder tree configured to generate a summation data element based on the plurality of output signals.

13. The neural network circuit of claim 11 , wherein
the sense amplifier circuit is configured to generate a plurality of analog signals based on the plurality of signals, and
the computation circuit comprises an analog-to-digital converter configured to, based on the plurality of analog signals and the input signal, perform one or more of a summation function, a scaling function, or a rectified linear unit function.

14. The neural network circuit of claim 11 , wherein the neural network circuit is configured to perform the matrix operation by generating the plurality of signals by sequentially selecting rows of DRAM cells of the array of DRAM cells.

15. The neural network circuit of claim 10 , wherein
the first circuit comprises a first semiconductor die,
the second circuit comprises a second semiconductor die, and
the plurality of via structures are positioned in one or more structural layers of an integrated circuit package comprising the first and second semiconductor dies.

16. A method of manufacturing an integrated circuit (IC) device, the method comprising:
building or packaging a dynamic random-access memory (DRAM) array in a first IC device layer;
building or packaging a computation circuit in a second IC device layer; and
forming via structures electrically connecting bit lines of the DRAM array to a sense amplifier circuit of the computation circuit,
wherein the forming the via structures electrically connecting the bit lines of the DRAM array to the sense amplifier circuit comprises electrically connecting an entirety of the bit lines electrically connected to the sense amplifier circuit.

17. The method of claim 16 , wherein
the building or packaging the DRAM array in the first IC device layer comprises packaging the DRAM array positioned in a first semiconductor wafer or die, and
the building or packaging the computation circuit in the second IC device layer comprises packaging the computation circuit positioned in a second semiconductor wafer or die.

18. The method of claim 16 , wherein
the building or packaging the DRAM array in the first IC device layer comprises building the DRAM array in a first layer of a partially processed semiconductor wafer, and
the building or packaging the computation circuit in the second IC device layer comprises building the computation circuit in a second layer of the partially processed semiconductor wafer.

19. The method of claim 16 , wherein the building or packaging the computation circuit comprises building or packaging a plurality of NOR gates coupled to the sense amplifier circuit and an adder tree circuit.

20.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chieh
• Huang Chia-En
• Liu Yi-Ching
• Cheng Wen-Chang
• Wang Yih

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title