Method and circuit to isolate body capacitance in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12381520-B2
Application number	US-202318513103-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Nov 15, 2018
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

First claim

What is claimed is:

1. An amplifying circuit, comprising:
a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first diode, wherein the first diode is formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated, and
a drain terminal and the body terminal of the first transistor are coupled together through a second diode; and

a common-source (CS) amplifier, wherein the CS amplifier comprises a second transistor connected in series with the first transistor, wherein the second transistor is further configured to receive an input voltage at a gate terminal of the CS amplifier.

2. The amplifying circuit of claim 1 , wherein
the second diode is formed between an N region of the drain terminal of the first transistor and the P-well region.

3. The amplifying circuit of claim 1 , wherein the first transistor comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

4. The amplifying circuit of claim 1 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

5. The amplifying circuit of claim 1 , wherein the CG amplifier is fabricated in a deep N well of a P-type substrate.

6. The amplifying circuit of claim 1 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

7. The amplifying circuit of claim 1 , wherein the second transistor is further configured to receive the input voltage at the gate terminal of the CS amplifier through a capacitor.

8. A power amplifying circuit, comprising:
a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first diode,
a drain terminal and the body terminal of the first transistor are coupled together through a second diode, and
the body terminal of the first transistor is coupled to ground; and

a common-source (CS) amplifier, wherein the CS amplifier comprises a second transistor that is connected in series with the first transistor, wherein the second transistor is further configured to receive an input voltage at a gate terminal of the CS amplifier through a capacitor and the gate terminal of the second transistor is coupled to an input voltage through the capacitor and is further coupled to an external bias voltage through a resistor.

9. The power amplifying circuit of claim 8 , wherein the first and second transistors each comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

10. The power amplifying circuit of claim 8 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

11. The power amplifying circuit of claim 8 , wherein the CG amplifier is fabricated in a deep N well of a P-type substrate.

12. The power amplifying circuit of claim 8 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

13. The power amplifying circuit of claim 8 , wherein the second diode is formed between an N region of the drain terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated.

14. The power amplifying circuit of claim 8 , wherein the first diode is formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated.

15. A method making an amplifying circuit, comprising:
forming a common-gate (CG) amplifier in a substrate, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first diode, the first diode formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated,
a drain terminal and the body terminal of the first transistor are coupled together through a second diode, the second diode formed between an N region of the drain terminal of the first transistor and the P-well region, and
the body terminal of the first transistor is further coupled to ground;

forming a common-source (CS) amplifier in the substrate, wherein the CS amplifier comprises a second transistor connected in series with the first transistor.

16. The method of claim 15 , wherein the first transistor comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

17. The method of claim 15 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

18. The method of claim 15 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

19. The method of claim 18 , wherein the second transistor is further configured to receive an input voltage at the gate terminal of the CS amplifier through a capacitor.

20. The method of claim 15 , wherein the CG amplifier is fabricated in a deep N well of a P-type substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liang Garming
• Chai Simon
• Yeh Tzu-Jin
• Yeh En-Hsiang
• Chen Wen-Sheng

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H03F2200/75

  the amplifier stage being a common source configuration MOSFET · CPC title

• H03F2200/72

  the amplifier stage being a common gate configuration MOSFET · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title