Low noise amplifier

Patent metadata

Field	Value
Publication number	US-2016126906-A1
Application number	US-201514931448-A
Country	US
Kind code	A1
Filing date	Nov 3, 2015
Priority date	Nov 3, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.

First claim

What is claimed is:

1 . Circuitry comprising:
a floating-body main field-effect transistor (FET) device comprising a gate contact, a drain contact, and a source contact; a body-contacted cascode FET device comprising a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device; and biasing circuitry coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.

2 . The circuitry of claim 1 wherein the biasing circuitry is configured to provide the biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that at least 75% of the supply voltage is provided across the body-contacted cascode FET device.

3 . The circuitry of claim 1 wherein the biasing circuitry is configured to provide the biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a drain-to-source voltage of the floating-body main FET device is less than about 1.5V.

4 . The circuitry of claim 3 wherein the supply voltage is between about 1.0V and 6.0V.

5 . The circuitry of claim 1 further comprising:
power supply circuitry configured to provide the supply voltage to the drain contact of the body-contacted cascode FET device;
an input node coupled to the gate contact of the floating-body main FET device; and
an output node coupled to the drain contact of the body-contacted FET device.

6 . The circuitry of claim 5 wherein the floating-body main FET device and the body-contacted cascode FET device are configured to amplify a signal provided at the input node using the supply voltage and provide the amplified input signal at the output node.

7 . The circuitry of claim 1 further comprising:
power supply circuitry configured to provide the supply voltage to the drain contact of the body-contacted cascode FET device;
an input node coupled to the source contact of the floating-body main FET device; and
an output node coupled to the drain contact of the body-contacted FET device.

8 . The circuitry of claim 1 wherein the floating-body main FET device and the body-contacted cascode FET device are thin-film silicon-on-insulator (SOI) devices.

9 . The circuitry of claim 8 wherein the floating-body main FET device and the body-contacted cascode FET device are metal-oxide-semiconductor field-effect transistor (MOSFET) devices.

10 . The circuitry of claim 9 wherein the floating-body main FET device and the body-contacted cascode FET device are monolithically integrated on a single semiconductor die.

11 . The circuitry of claim 10 wherein the floating-body main FET device shares at least one diffusion with the body-contacted cascode FET device.

12 . Circuitry comprising:
one or more floating-body main field-effect transistor (FET) devices; one or more body-contacted cascode FET devices coupled in series between a supply voltage and the one or more floating-body main FET devices; and biasing circuitry coupled to a gate contact of each of the one or more floating body main FET devices and a gate contact of each of the one or more body-contacted cascode FET devices and configured to provide biasing signals to each of the one or more floating-body main FET devices and each of the one or more body-contacted cascode FET devices such that a source-to-drain voltage of each of the one or more floating-body main FET devices is less than about 1.5V.

13 . The circuitry of claim 12 wherein the supply voltage is between about 1.0V and 6.0V.

14 . The circuitry of claim 12 wherein the one or more floating-body main FET devices and the one or more body-contacted cascode FET devices are thin-film silicon-on-insulator (SOI) devices.

15 . The circuitry of claim 12 further comprising:
power supply circuitry configured to provide the supply voltage;
an input node coupled to a gate contact of a first one of the one or more floating-body main FET devices; and
an output node coupled to a drain contact of a last one of the one or more body-contacted FET devices.

16 . The circuitry of claim 15 wherein the one or more floating-body main FET devices and the one or more body-contacted cascode FET devices are configured to amplify a signal provided at the input node using the supply voltage and provide the amplified input signal at the output node.

17 . The circuitry of claim 12 wherein the one or more floating-body main FET devices and the one or more body-contacted cascode FET devices are thin-film silicon-on-insulator (SOI) devices.

18 . The circuitry of claim 17 wherein the one or more floating-body main FET devices and the one or more body-contacted cascode FET devices are metal-oxide-semiconductor field-effect transistor (MOSFET) devices.

19 . The circuitry of claim 18 wherein the one or more floating-body main FET devices and the one or more body-contacted cascode FET devices are monolithically integrated on a single semiconductor die.

20 . The circuitry of claim 19 wherein each of the one or more floating-body main FET devices shares at least one diffusion with one of the one or more body-contacted FET devices.

Assignees

• Rf Micro Devices Inc

Inventors

• Maxim George
• Leipold Dirk Robert Walter
• Scott Baker
• Nieri Ralph Christopher

Classifications

• H03F2200/492

  A coil being added in the source circuit of a transistor amplifier stage as degenerating element · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H04B1/1036

  with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters (H04B1/123 takes precedence; filter circuits H03H) · CPC title

• H03F3/193 Primary

  with field-effect devices (H03F3/195 takes precedence) · CPC title