Voltage generator and memory device including the same

Patent metadata

Field	Value
Publication number	US-12380953-B2
Application number	US-202318184842-A
Country	US
Kind code	B2
Filing date	Mar 16, 2023
Priority date	Mar 23, 2022
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A memory device includes a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array including a plurality of memory cells, and a peripheral circuit region under the memory cell array region, wherein the memory cell array region and the peripheral circuit region are electrically connected by through vias, the peripheral circuit region includes a voltage generator configured to generate an operating voltage to apply to the word lines, the voltage generator includes a pumping capacitor unit configured to charge and pump a voltage based on a clock signal, and a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller includes a clock driver configured to apply a clock signal to the pumping capacitor, and the signal controller is adjacent to the through vias.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array region comprising a plurality of memory cells stacked vertically on a substrate; and
a peripheral circuit region under the memory cell array region, wherein
the memory cell array region and the peripheral circuit region are electrically connected to each other by through vias extending in a first direction,
the peripheral circuit region comprises a voltage generator configured to generate an operating voltage to apply to the word lines to operate the memory cells,
the voltage generator comprises
a pumping capacitor unit including one or more pumping capacitors configured to perform charge pumping to charge and pump a voltage based on a clock signal, and
a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller being adjacent to the through vias, the signal controller comprising
a clock driver configured to apply a clock signal to the pumping capacitor unit, and
a high-voltage transistor configured to pre-charge the pumping capacitor unit to a first voltage, and

a first distance between the through vias and the signal controller in a second direction is smaller than a second distance between the through vias and the one or more pumping capacitors in the second direction, and the second direction is perpendicular to the first direction.

2. The memory device of claim 1 , wherein
the signal controller further comprises a plurality of charge transfer switches configured to control the current flowing through the pumping capacitor unit.

3. The memory device of claim 2 , wherein
the clock driver receives power through the through vias to generate a clock signal, and
a third distance between the through vias and the clock driver in the second direction is smaller than a fourth distance between the through vias and the plurality of charge transfer switches in the second direction.

4. The memory device of claim 2 , wherein
the plurality of charge transfer switches comprise an NMOS transistor and a PMOS transistor, and
a third distance between the one or more pumping capacitors and the NMOS transistor in the second direction is greater than a fourth distance between the one or more pumping capacitors and the PMOS transistor in the second direction.

5. The memory device of claim 1 , wherein
the signal controller comprises
a plurality of charge transfer switches configured to control a second current applied to the pumping capacitor unit, and

the pumping capacitor unit comprises
a plurality of pumping capacitors configured to perform charge pumping in response to a plurality of clock signals, and
a gate pumping capacitor connected to a gate of one of the plurality of charge transfer switches.

6. The memory device of claim 5 , wherein
the clock driver is configured to receive power through the through vias to generate a clock signal, and
a third distance between the through vias and the clock driver in the second direction is smaller than a fourth distance between the through vias and the plurality of charge transfer switches in the second direction.

7. The memory device of claim 5 , wherein
the clock driver is configured to receive power through the through vias to generate a clock signal, and
a third distance between the through vias and the clock driver in the second direction is smaller than a fourth distance between the through vias and the high-voltage transistor in the second direction.

8. The memory device of claim 5 , wherein
the pumping capacitor unit comprises a high-voltage device, and
a third distance between the high-voltage transistor and the pumping capacitor unit in the second direction is smaller than a fourth distance between the charge transfer switches and the pumping capacitor unit in the second direction.

9. The memory device of claim 5 , wherein
a third distance between the high-voltage transistor and the pumping capacitor unit in the second direction is greater than a fourth distance between the charge transfer switches and the pumping capacitor unit in the second direction, and
a first body voltage of the pumping capacitor unit and a second body voltage of the high-voltage transistor are not shared.

10. The memory device of claim 5 , wherein the plurality of charge transfer switches and the clock driver are arranged adjacent to each other in the first direction in the signal controller.

11. The memory device of claim 1 , wherein the pumping capacitor is a metal-insulator-metal (MIM) capacitor.

12. A voltage generator comprising:
first to n-th pumping stages, wherein
n is a natural number equal to or greater than 2,
the first pumping stage comprises a first pumping capacitor unit and a first signal controller,
the n-th pumping stage comprises an n-th pumping capacitor unit and an n-th signal controller,
the first to n-th pumping stages are arranged side-by-side in a first direction,
the first pumping capacitor unit and the first signal controller are arranged side-by-side in a second direction perpendicular to the first direction in the first pumping stage,
the n-th pumping capacitor unit and the n-th signal controller are arranged side-by-side in a second direction perpendicular to the first direction in the n-th pumping stage,
the first signal controller comprises a plurality of first charge transfer switches and a first clock driver configured to apply a clock signal to the first pumping capacitor unit,
the n-th signal controller comprises a plurality of n-th charge transfer switches and an n-th clock driver configured to apply a clock signal to the n-th pumping capacitor unit,
the plurality of first charge transfer switches are arranged between the first clock driver and the first pumping capacitor unit,
the plurality of n-th charge transfer switches are arranged between the n-th clock driver and the n-th pumping capacitor unit,
the first to n-th clock drives are configured to receive power from through vias,
a first distance between the through vias and a first clock driver in the second direction is same as a second distance between the through vias and a second clock driver in the second direction,
the first signal controller comprises a first high-voltage transistor, and
the n-th signal controller comprises an n-th high-voltage transistor.

13. The voltage generator of claim 12 , wherein
the first clock driver, a first charge transfer switch, and a first high-voltage transistor are sequentially arranged in the second direction in the first signal controller, and
the n-th clock driver, an n-th charge transfer switch, and an n-th high-voltage transistor are sequentially arranged in the second direction in the n-th signal controller.

14. The voltage generator of claim 13 , wherein
the first charge transfer switch comprises a first NMOS transistor and a first PMOS transistor,
the n-th charge transfer switch comprises an n-th NMOS transistor and an n-th PMOS transistor,
in the first signal controller, the first clock driver, the first NMOS transistor, the first PMOS transistor, and the first high-voltage transistor are sequentially arranged in the second direction, and
the n-th signal controller, the n-th clock driver, the n-th NMOS transistor, the n-th PMOS transistor, and the n-th high-voltage transistor are sequentially arranged in the second direction.

15. The voltage generator of claim 12 , wherein
an m-th pumping stage is included in the first to n-th p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yoonjae
• Yoo Byungjoon
• Yoon Chiweon
• Lee Cheonan

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G11C16/32

  Timing circuits · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title