Oscillator circuit with location-based charge pump enable and semiconductor memory including the same

Patent metadata

Field	Value
Publication number	US-9093167-B2
Application number	US-201213685493-A
Country	US
Kind code	B2
Filing date	Nov 26, 2012
Priority date	Nov 26, 2012
Publication date	Jul 28, 2015
Grant date	Jul 28, 2015

Abstract

A semiconductor memory includes a plurality of memory blocks each comprising a plurality of memory cells, and a plurality of charge pumps each located near one of the plurality of memory blocks. In an access to the semiconductor memory, depending on the selected memory block, a subset or all of the plurality of charge pumps are activated in one of a predetermined number of sequences.

First claim

What is claimed is:

1. A semiconductor memory, comprising:
a plurality of memory blocks each comprising a plurality of memory cells; and
a plurality of charge pumps each located near one of the plurality of memory blocks,
wherein in an access to the semiconductor memory, depending on the selected memory block, a subset or all of the plurality of charge pumps are activated in one of a predetermined number of sequences.

2. The semiconductor memory of claim 1 wherein in a first activation cycle of each of the predetermined number of sequences, less than all of the plurality of charge pumps are activated.

3. The semiconductor memory of claim 2 wherein in each of the predetermined number of sequences, at least the charge pump located closest to the selected memory block is activated in the first activation cycle.

4. The semiconductor memory of claim 1 wherein in at least one of the predetermined number of sequences, at least one charge pump located closest to the selected memory block is activated in a first activation cycle.

5. The semiconductor memory of claim 1 wherein after a first activation cycle, no two or more of the plurality of charge pumps are activated at the same time.

6. The semiconductor memory of claim 1 wherein in at least one of the predetermined number of sequences, no two or more of the plurality of charge pumps are activated at the same time.

7. The semiconductor memory of claim 1 wherein in at least one of the predetermined number of sequences, at least one of the plurality of charge pumps remains deactivated.

8. The semiconductor memory of claim 1 further comprising:
a ring oscillator comprising delay blocks coupled in a ring formation; and
a logic block configured to receive signals from intermediate nodes of the ring oscillator as well as block select signals indicating which of the plurality of memory blocks is selected in an access to the memory, and in response generate pump enable signals for activating the plurality of charge pumps in one of the predetermined number of sequences.

9. The semiconductor memory of claim 8 further comprising a plurality of reset circuits each coupled to a different node in the ring oscillator, each reset circuit including a one-shot pulse generator configured to generate a pulse in response to a block select signal, wherein the reset circuit forces the potential at the oscillator node to which it is coupled to a predetermined voltage level for the duration of the pulse.

10. The semiconductor memory of claim 1 wherein each of the plurality of charge pumps has an output terminal, wherein the output terminal of the plurality of charge pumps are connected together.

11. A method of operating a semiconductor memory comprising a plurality of charge pumps each located near one of a plurality of memory blocks, the method comprising:
accessing one of the plurality of memory blocks; and
activating a subset or all of the plurality of charge pumps in one of a predetermined number of sequences.

12. The method of claim 11 wherein in a first activation cycle of each of the predetermined number of sequences, less than all of the plurality of charge pumps are activated.

13. The method of claim 12 wherein in each of the predetermined number of sequences, at least the charge pump located closest to the selected memory block is activated in the first activation cycle.

14. The method of claim 11 wherein in at least one of the predetermined number of sequences, only the charge pump located closest to the selected memory block is activated in a first activation cycle.

15. The method of claim 11 wherein after a first activation cycle, no two or more of the plurality of charge pumps are activated at the same time.

16. The method of claim 11 wherein in at least one of the predetermined number of sequences, no two or more of the plurality of charge pumps are activated at the same time.

17. The method of claim 11 wherein in at least one of the predetermined number of sequences, two charge pumps located closest to the selected bank are activated in a first activation cycle.

18. The method of claim 11 wherein in at least one of the predetermined number of sequences, at least one of the plurality of charge pumps remains deactivated.

19. The method of claim 11 wherein the semiconductor memory further includes a ring oscillator having delay blocks coupled in a ring formation, and a logic block coupled to the ring oscillator, the method further comprising:
receiving a first group of signals from intermediate nodes of the ring oscillator at a first group of input terminals of the logic block;
receiving block select signals at a second group of input terminals of the logic block, the block select signals indicating which of the plurality of the memory blocks is selected in an access to the memory; and
in response to the first group of signals and the block select signals, generating pump enable signals at output terminals of the logic block, for activating the plurality of charge pumps in one of the predetermined number of sequences.

20. The method of claim 19 wherein the semiconductor memory further includes a plurality of reset circuits each coupled to a different node in the ring oscillator, and each reset circuit includes a one-shot pulse generator, the method further comprising:
generating a pulse at an output terminal of one of the one-shot pulse generators in response to a block select signal, wherein the corresponding reset circuit forces the potential at the oscillator node to which it is coupled to a predetermined voltage level for the duration of the pulse.

Assignees

• Sk Hynix Inc

Inventors

• Jung Taehyung

Classifications

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title