Semiconductor devices including cell-type power decoupling capacitors

Patent metadata

Field	Value
Publication number	US-9305919-B2
Application number	US-201313792867-A
Country	US
Kind code	B2
Filing date	Mar 11, 2013
Priority date	Apr 2, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor device includes an internal circuit and a cell-type power decoupling capacitor. The cell-type power decoupling capacitor is formed on a semiconductor substrate using a stack cell capacitor process. The cell-type power decoupling capacitor stabilizes a supply voltage to provide the stabilized supply voltage to the internal circuit. Accordingly, the semiconductor device including the cell-type power decoupling capacitor may be insensitive to power noise and may occupy a small area on a chip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an internal circuit in the substrate; and
a cell-type power decoupling capacitor on the internal circuit, the cell-type power decoupling capacitor stabilizing a supply voltage to provide the stabilized supply voltage to the internal circuit;
wherein the cell-type power decoupling capacitor comprises:
a first conductive layer connected to a first supply voltage;
a second conductive layer connected to a second supply voltage that is lower than the first supply voltage, and separated from the first conductive layer; and
a dielectric layer disposed between the first conductive layer and the second conductive layer,
wherein the cell-type power decoupling capacitor is on a metal-oxide-semiconductor field-effect transistor (MOSFET).

2. The semiconductor device according to claim 1 , wherein the first conductive layer and the second conductive layer comprise poly-silicon layers.

3. The semiconductor device according to claim 1 , wherein the semiconductor device comprises a semiconductor memory device.

4. The semiconductor device according to claim 1 , wherein the second conductive layer comprises a U-shape structure.

5. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is on a resistor that is disposed in the substrate.

6. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is on a poly-silicon layer disposed in the substrate.

7. A semiconductor device, comprising:
a substrate;
an internal circuit in the substrate; and
a cell-type power decoupling capacitor on the internal circuit, the cell-type power decoupling capacitor stabilizing a supply voltage to provide the stabilized supply voltage to the internal circuit;
wherein the cell-type power decoupling capacitor comprises:
a first conductive layer connected to a first supply voltage;
a second conductive layer connected to a second supply voltage that is lower than the first supply voltage, and separated from the first conductive layer; and
a dielectric layer disposed between the first conductive layer and the second conductive layer,
wherein the cell-type power decoupling capacitor is on an N-type well or a P-type well, the N-type well or the P-type well disposed in the substrate.

8. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is on areas between CMOS transistor arrays.

9. The semiconductor device according to claim 8 , wherein the cell-type power decoupling capacitor is on areas between two adjacent CMOS transistor arrays.

10. The semiconductor device according to claim 8 , wherein the cell-type power decoupling capacitor is on areas between every N CMOS transistor arrays, wherein N is an integer equal to or larger than two.

11. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is under a metal fuse.

12. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is under a pad metal.

13. The semiconductor device according to claim 1 , wherein the cell-type power decoupling capacitor is on a poly-silicon layer, the poly-silicon layer comprising a pumping capacitor.

14. A semiconductor device, comprising:
a substrate;
a plurality of first circuit elements in the substrate;
a plurality of power decoupling capacitor cells on the plurality of first circuit elements, remote from the substrate; and
a plurality of second circuit elements on the plurality of power decoupling capacitor cells, remote from the plurality of first circuit elements.

15. The semiconductor device according to claim 14 , wherein the plurality of first circuit elements comprise a plurality of N-type transistors, a plurality of P-type transistors, a plurality of CMOS transistors, a plurality of resistors and/or a plurality of pumping capacitors.

16. The semiconductor device according to claim 14 , wherein the plurality of second circuit elements comprise a plurality of pads and/or a plurality of fuses.

17. The semiconductor device according to claim 14 , wherein the plurality of power decoupling capacitor cells comprise a plurality of electrodes that extend along a face of the substrate and also extend orthogonal to the face of the substrate.

18. The semiconductor device according to claim 14 , wherein the plurality of power decoupling capacitor cells comprise first and second poly-silicon layers with a dielectric layer therebetween.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Han-Sik
• Oh Se-Il

Classifications

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D84/212 Primary

  of only capacitors · CPC title

• H01L27/0805 Primary

  Electricity · mapped topic

• H01L28/90

  Electricity · mapped topic