Voltage doubler and nonvolating memory device having the same

Patent metadata

Field	Value
Publication number	US-9369115-B2
Application number	US-201514637670-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Apr 7, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.

First claim

What is claimed is:

1. A voltage doubler comprising:
a first transistor connected between a first node and an input terminal configured to receive an input voltage;
a second transistor connected between the input terminal and a second node;
a third transistor connected between the first node and an output terminal configured to output an output voltage;
a fourth transistor connected between the second node and the output terminal;
a first capacitor connected between the first node and a first clock terminal configured to receive a first clock signal;
a second capacitor connected between the second node and a second clock terminal configured to receive an inverted first clock signal;
a first gate control unit configured to control the first and second transistors using the first clock signal and the inverted first clock signal;
a second gate control unit configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal; and
a load capacitor connected between the output terminal and a ground terminal.

2. The voltage doubler of claim 1 , wherein each of the first and second transistors comprises an NMOS transistor and each of the third and fourth transistors comprises a PMOS transistor.

3. The voltage doubler of claim 1 , wherein the second clock signal is obtained by delaying the first clock signal by a predetermined time.

4. The voltage doubler of claim 1 , wherein the first gate control unit comprises:
first boosting capacitors connected to gates of the first and second transistors and configured to receive the first clock signal and the inverted first clock signal; and
a pair of NMOS transistors cross-coupled between the gates of the first and second transistors and the input terminal.

5. The voltage doubler of claim 1 , wherein the second gate control unit comprises:
second boosting capacitors connected to gates of the third and fourth transistors and configured to receive the second clock signal and the inverted second clock signal; and
a pair of PMOS transistors cross-coupled between the gates of the third and fourth transistors and the output terminal.

6. The voltage doubler of claim 1 , further comprising:
a first diode connected between the second node and a gate of the third transistor; and
a second diode connected between the first node and a gate of the fourth transistor.

7. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory blocks each formed of a plurality of memory cells;
an address decoder configured to select one of the plurality of memory blocks;
a voltage generation circuit configured to provide a word line voltage to word lines of the selected memory block;
an input/output circuit configured to store page data to be programmed at a selected page of the selected memory block at a program operation and store data read from the selected page of the selected memory block at a read operation; and
a control circuit configured to control the address decoder, the voltage generation circuit, and the input/output circuit;
wherein the voltage generation circuit comprises a voltage doubler including
a first transistor connected between a first node and an input terminal configured to receive an input voltage,
a second transistor connected between the input terminal and a second node,
a third transistor connected between the first node and an output terminal configured to output an output voltage,
a fourth transistor connected between the second node and the output terminal,
a first capacitor connected between the first node and a first clock terminal configured to receive a first clock signal,
a second capacitor connected between the second node and a second clock terminal configured to receive an inverted first clock signal,
a first gate control unit configured to control the first and second transistors using the first clock signal and the inverted first clock signal,
a second gate control unit configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal, and
a load capacitor connected between the output terminal and a ground terminal.

8. The nonvolatile memory device of claim 7 , wherein each of the memory blocks includes strings formed between a common source line and bit lines and in a direction perpendicular to a substrate.

9. The nonvolatile memory device of claim 8 , wherein word lines and/or the bit lines are shared between levels.

10. The nonvolatile memory device of claim 7 , wherein the first gate control unit comprises:
first boosting capacitors connected to gates of the first and second transistors and configured to receive the first clock signal and the inverted first clock signal; and
a pair of NMOS transistors cross-coupled between the gates of the first and second transistors and the input terminal.

11. The nonvolatile memory device of claim 7 , wherein the second gate control unit comprises:
second boosting capacitors connected to gates of the third and fourth transistors and configured to receive the second clock signal and the inverted second clock signal; and
a pair of PMOS transistors cross-coupled between the gates of the third and fourth transistors and the output terminal.

12. The nonvolatile memory device of claim 7 , wherein the voltage doubler further comprises:
a first diode connected between the second node and a gate of the third transistor; and
a second diode connected between the first node and a gate of the fourth transistor.

13. The nonvolatile memory device of claim 7 , wherein the second clock signal is obtained by delaying the first clock signal by a predetermined time.

14. The nonvolatile memory device of claim 7 , wherein each of the memory cells includes a charge trap layer.

15. A method of making a voltage doubler, the method comprising:
connecting a first transistor between a first node and an input terminal configured to receive an input voltage;
connecting a second transistor between the input terminal and a second node;
connecting a third transistor between the first node and an output terminal configured to output an output voltage;
connecting a fourth transistor between the second node and the output terminal;
connecting a first capacitor between the first node and a first clock terminal configured to receive a first clock signal;
connecting a second capacitor between the second node and a second clock terminal configured to receive an inverted first clock signal;
providing a first gate control unit to control the first and second transistors using the first clock signal and the inverted first clock signal;
providing a second gate control unit to control the third and fourth transistors using a second clock signal and an inverted second clock signal; and
connecting a load capacitor between the output terminal and a ground terminal.

16. The method of claim 15 , wherein each of the first and second transistors comprises an NMOS transistor and each of the third and fourth transistors comprises a PMOS transistor.

17. The method of claim 15 , wherein the second clock signal is obtained by delaying the first clock signal by a predetermined time.

18. The method of claim 15 , wherein providing the first gate control unit comprises:
connecting first boosting capacitors to gates of the first and second transistors and configured to receive the first clock signal and the inverted first clock signal; and
cross-coupling a pair of NMOS transistors between the gates of the first and second transis

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kalluru Vivek Venkata
• Min Youngsun
• Lee Hichoon

Classifications

• H03K5/023 Primary

  using field effect transistors · CPC title

• Y10T29/49169

  Assembling electrical component directly to terminal or elongated conductor · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title