Silicide backside contact

Patent metadata

Field	Value
Publication number	US-12376360-B2
Application number	US-202218074317-A
Country	US
Kind code	B2
Filing date	Dec 2, 2022
Priority date	Nov 24, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

First claim

What is claimed is:

1. A method, comprising:
receiving a workpiece comprising:
a fin-shaped structure over a substrate, the fin-shaped structure comprising a plurality of channel layers, and
a first dummy gate stack and a second dummy gate stack over the fin-shaped structure;

forming a source opening in the fin-shaped structure between the first dummy gate stack and the second dummy gate stack to expose sidewalls of the fin-shaped structure;
extending the source opening into the substrate to form an extended source opening;
forming a semiconductor plug into the extended source opening;
forming a source feature over the exposed sidewalls of the plurality of channel layers and the semiconductor plug in the extended source opening;
planarizing the substrate to expose the semiconductor plug;
after the planarizing, replacing the substrate with a backside dielectric layer;
depositing a metal layer over the backside dielectric layer and the exposed semiconductor plug; and
performing a first anneal process to bring about silicidation between the metal layer and the exposed semiconductor plug.

2. The method of claim 1 , wherein the semiconductor plug comprises silicon germanium (SiGe).

3. The method of claim 1 , wherein the metal layer comprises nickel, platinum, or titanium.

4. The method of claim 1 , further comprising:
after the performing of the first anneal process, performing a wet etch process until the backside dielectric layer is exposed; and
after the performing of the wet etch process, performing a second anneal process.

5. The method of claim 4 , wherein the wet etch process comprises use of hydrogen peroxide (H 2 O 2 ), hydrofluoric acid (HF), nitric acid (HNO 3 ), hydrochloric acid (HCl), sulfuric acid (H 2 SO 4 ) or a ferric chloride (FeCl 3 ) solution.

6. The method of claim 4 ,
wherein the first anneal process comprises a first annealing temperature,
wherein the second anneal process comprises a second annealing temperature greater than the first annealing temperature.

7. The method of claim 6 ,
wherein the first annealing temperature is between about 200° C. and about 300° C.,
wherein the second annealing temperature is between about 300° C. and about 400° C.

8. The method of claim 1 , wherein the replacing of the substrate comprises:
etching back the exposed semiconductor plug;
forming a hard mask feature over the etched-back semiconductor plug;
anisotropically etching the substrate using the hard mask feature as an etch mask; and
after the anisotropically etching, depositing the backside dielectric layer.

9. The method of claim 8 , wherein the replacing of the substrate further comprises:
after the depositing of the backside dielectric layer, planarizing the backside dielectric layer to expose the semiconductor plug.

10. The method of claim 8 ,
wherein the anisotropically etching leaves behind a portion of the substrate extending along sidewalls of the etched-back semiconductor plug,
wherein the first anneal process further brings about silicidation between the metal layer and the portion of the substrate.

11. A method, comprising:
forming, over a front side of a substrate, a fin-shaped structure comprising a first channel region, a second channel region, and a source/drain region between the first channel region and the second channel region;
etching the source/drain region of the fin-shaped structure to form an extended opening that extends into the substrate;
forming a semiconductor plug in the extended opening while sidewalls of the fin-shaped structure in the first channel region and the second channel region are exposed;
forming an epitaxial feature over the semiconductor plug to be in contact with the exposed sidewalls of the fin-shaped structure in the first channel region and the second channel region;
performing a first planarization process to a back side of the substrate to expose the semiconductor plug;
after the first planarization process, etching back the semiconductor plug to form a recess;
forming a hard mask layer in the recess to cover the etched-back semiconductor plug;
after the forming of the hard mask layer, removing the substrate;
after the removing of the substrate, depositing a backside dielectric layer over the hard mask layer;
performing a second planarization process to the backside dielectric layer to expose the etched-back semiconductor plug;
depositing a metal layer over the backside dielectric layer and the exposed semiconductor plug; and
performing a first anneal process to bring about silicidation between the metal layer and the exposed semiconductor plug to form a silicide feature.

12. The method of claim 11 ,
wherein the fin-shaped structure comprises a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers,
wherein a composition of the plurality of first semiconductor layers is different from a composition of the plurality of second semiconductor layers.

13. The method of claim 11 , further comprising:
etching back the silicide feature until the backside dielectric layer is exposed to form a backside contact in the backside dielectric layer; and
performing a second anneal process to improve a conductivity of the backside contact.

14. The method of claim 13 , wherein the etching back of the silicide feature comprises a wet etch process.

15. The method of claim 13 ,
wherein the first anneal process comprises a first annealing temperature,
wherein the second anneal process comprises a second annealing temperature greater than the first annealing temperature.

16. The method of claim 13 , further comprising:
forming a backside rail over the backside contact.

17. A method, comprising:
receiving a workpiece comprising:
a fin-shaped structure over a front side of a substrate and comprising a first channel region, a second channel region, and a source/drain region between the first channel region and the second channel region,
a first dummy gate stack over the first channel region, and
a second dummy gate stack over the second channel region;

depositing a gate spacer layer over the workpiece;
after the depositing of the gate spacer layer, forming an extending opening through the source/drain region and into the substrate below the source/drain region;
forming a semiconductor plug in the extended opening;
forming an epitaxial feature over the semiconductor plug, the epitaxial feature being in contact with sidewalls of the fin-shaped structure in the first channel region and the second channel region;
after the forming of the epitaxial feature, replacing the first dummy gate stack and the second dummy gate stack with a first metal gate structure and a second metal gate structure, respectively,
performing a first planarization process to a back side of the substrate to expose the semiconductor plug;
forming a hard mask layer to cover the semiconductor plug;
after the forming of the hard mask layer, removing the substrate;
after the removing of the substrate, depositing a backside dielectric layer over the hard mask layer;
performing a second planarization process to the backside dielectric layer to expose the semiconductor plug;
depositing a metal layer over the backside dielectric layer and the exposed semiconductor plug; and
performing a first anneal process to bring about silicidation between the metal layer and the exposed semiconductor plug to form a silicide feature.

18. The method of claim 17 , wherein the fin-shaped structure comprises a plurality of channel layers int

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Chen-Hung
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D84/834

  comprising FinFETs · CPC title