Method of forming backside power rails

Patent metadata

Field	Value
Publication number	US-11411100-B2
Application number	US-202017037274-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Sep 29, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

First claim

What is claimed is:

1. A method, comprising:
forming a composite substrate that includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer;
forming a fin structure from the fourth semiconductor layer;
forming a dummy gate stack over a channel region of the fin structure;
recessing a source region and a drain region of the fin structure to form a source opening and a drain opening, the channel region being disposed between the source region and the drain region;
selectively etching the source region of the fin structure to extend the source opening through the third semiconductor layer to form an extended source opening;
selectively forming a semiconductor plug into the extended source opening;
planarizing the composite substrate to remove the substrate, the first semiconductor layer, and the second semiconductor layer to expose the semiconductor plug;
after the planarizing, replacing the third semiconductor layer with a dielectric layer; and
replacing the semiconductor plug with a backside source contact.

2. The method of claim 1 ,
wherein the first semiconductor layer and the third semiconductor layer have the same composition,
wherein the second semiconductor layer and the fourth semiconductor layer have the same composition.

3. The method of claim 1 ,
wherein the first semiconductor layer comprises silicon germanium,
wherein the second semiconductor layer comprises silicon,
wherein the third semiconductor layer comprises silicon germanium,
wherein the fourth semiconductor layer comprises silicon.

4. The method of claim 1 , wherein the source opening and the drain opening do not extend into the third semiconductor layer.

5. The method of claim 1 , wherein the extended source opening terminates in the second semiconductor layer.

6. The method of claim 1 , wherein the selectively etching of the source region comprises masking the drain opening with a photoresist layer.

7. The method of claim 1 , wherein the semiconductor plug comprises silicon.

8. The method of claim 1 , wherein the replacing of the semiconductor plug with the backside source contact comprises selectively etching the semiconductor plug without substantially etching the dielectric layer.

9. A method, comprising:
forming a composite substrate that includes a substrate, a first silicon germanium (SiG) layer over the substrate, a first silicon (Si) layer over the first SiGe layer, a second SiGe layer over the first Si layer, and a second Si layer over the second SiGe layer;
forming a fin structure from the second Si layer;
forming a dummy gate stack over a channel region of the fin structure;
recessing a source region and a drain region of the fin structure to form a source opening and a drain opening, the channel region being disposed between the source region and the drain region;
selectively etching the source region of the fin structure to extend the source opening through the second SiGe layer to form an extended source opening;
selectively forming a Si plug into the extended source opening;
after the selective forming of the Si plug, forming a source feature over the Si plug and a drain feature in the drain opening;
planarizing the composite substrate to remove the substrate, the first SiGe layer, and the first Si layer to expose the Si plug;
after the planarizing, replacing the second SiGe layer with a dielectric layer; and
replacing the Si plug with a backside source contact.

10. The method of claim 9 , wherein the source opening and the drain opening do not extend into the second SiGe layer.

11. The method of claim 9 , wherein the extended source opening terminates in the first Si layer.

12. The method of claim 9 , wherein the selectively etching of the source region comprises masking the drain opening with a photoresist layer.

13. The method of claim 9 , wherein the dielectric layer comprises silicon oxide.

14. The method of claim 9 , wherein each of the first SiGe layer and the second SiGe layer comprises a thickness between about 25 nm and about 35 nm.

15. The method of claim 9 , wherein the replacing of the Si plug with the backside source contact comprises selectively etching the Si plug to expose the source feature in a backside source contact opening.

16. The method of claim 15 , wherein the replacing of the Si plug with the backside source contact further comprises:
selectively forming a silicide layer over the exposed source feature; and
depositing a metal fill layer in the backside source contact opening.

17. A semiconductor structure, comprising:
a source feature and a drain feature;
a first channel structure disposed between the source feature and the drain feature along a direction;
a second channel structure adjacent the source feature such that the source feature is sandwiched between the first channel structure and the second channel structure along the direction;
a dielectric layer disposed over the drain feature;
a backside source contact over the source feature and extending through the dielectric layer; and
a backside power rail disposed over the dielectric layer and in contact with the backside source contact,
wherein a portion of the backside source contact is disposed between the first channel structure and the second channel structure along the direction.

18. The semiconductor structure of claim 17 , further comprising a silicide layer sandwiched between the source feature and the backside source contact.

19. The semiconductor structure of claim 17 ,
wherein the drain feature is spaced apart from the dielectric layer by a bottom semiconductor feature,
wherein the bottom semiconductor feature is integral with the channel structure.

20. The semiconductor structure of claim 19 , wherein the bottom semiconductor feature comprises silicon.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Ping-Wei
• Yang Chih-Chuan
• Lin Yu-Kuan
• Yeap Choh Fei

Classifications

• H10W72/07341

  Controlling the bonding environment, e.g. atmosphere composition or temperature · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title