Self-aligned contact air gap formation

Patent metadata

Field	Value
Publication number	US-12376351-B2
Application number	US-202418439095-A
Country	US
Kind code	B2
Filing date	Feb 12, 2024
Priority date	Sep 27, 2018
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

First claim

What is claimed is:

1. A device comprising:
a source/drain feature disposed on a substrate;
a gate stack disposed on the substrate and associated with the source/drain feature;
a first interlayer dielectric layer disposed on the substrate;
a contact feature extending through the first interlayer dielectric layer to the source/drain feature;
a nitride layer disposed directly on and extending along a sidewall of the contact feature to the source/drain feature;
a silicon-containing layer disposed directly on and extending along a sidewall of the nitride layer to the source/drain feature; and
a seal layer disposed directly on the first interlayer dielectric layer, the nitride layer and the contact feature, the seal layer sealing an air gap defined by the nitride layer, the silicon-containing layer, the sealing layer and the first interlayer dielectric layer, wherein the nitride layer, the silicon-containing layer, the sealing layer and the first interlayer dielectric layer are exposed to the air gap.

2. The device of claim 1 , wherein the nitride layer extends continuously from the seal layer to the source/drain feature.

3. The device of claim 1 , further comprising:
a first etch stop layer disposed directly on the silicon layer, and
a second etch stop layer dispose directly on the gate stack, and
wherein the first and second etch stop layers are exposed to the air gap.

4. The device of claim 3 , wherein the first etch stop layer extends to the source/drain feature.

5. The device of claim 1 , wherein the gate stack extends to a first height above the substrate and the silicon-containing layer extends to a second height above the substrate that is different than the first height.

6. The device of claim 5 , wherein the first height is greater than the second height.

7. The device of claim 1 , wherein the silicon-containing layer includes a material selected from the group consisting of silicon germanium, silicon nitride and silicon oxide.

8. A device comprising:
a source/drain feature disposed on a substrate;
a gate stack disposed on the substrate and associated with the source/drain feature, the gate stack extending to a first height above the substrate;
a first interlayer dielectric layer disposed on the substrate;
a contact feature extending through the first interlayer dielectric layer to the source/drain feature;
an air gap disposed between the gate stack and the contact feature, the air gap extending from the source/drain feature to a second height above the substrate that is different than the first height of the gate stack, the source/drain feature being exposed to the air gap; and
a nitride layer disposed directly on and extending along a sidewall of the contact feature, the nitride layer having a bottom surface facing the substrate and wherein the bottom surface of the nitride layer is exposed to the air gap.

9. The device of claim 8 , wherein the second height is greater than the first height.

10. The device of claim 8 , further comprising a seal layer disposed directly on the first interlayer dielectric layer and the nitride layer, the seal layer sealing the air gap defined by the nitride layer, the seal layer, the first interlayer dielectric layer and the source/drain feature, wherein the nitride layer, the seal layer and the first interlayer dielectric layer are exposed to the air gap.

11. The device of claim 10 , wherein the seal layer includes a first portion on a first side of the contact feature and a second portion on a second side of the contact feature,
wherein the first portion of the seal layer extends closer to the substrate than the second portion of the seal layer, and
wherein the first portion and the second portion of the seal layer are exposed to the air gap.

12. The device of claim 11 , wherein the first portion of the seal layer is wider than the second portion of the seal layer.

13. The device of claim 8 , wherein the source/drain feature includes a silicide feature that is exposed to the air gap.

14. The device of claim 13 , wherein the source/drain feature further includes a doped region that is exposed to the air gap, the doped region being different than the silicide feature.

15. The device of claim 8 , wherein the nitride layer includes a carbon-doped SiN material.

16. A device comprising:
a source/drain feature disposed on a substrate;
a first gate stack disposed on the substrate and associated with the source/drain feature, wherein the first gate stack includes a conductive layer and a sidewall spacer;
a second gate stack disposed on the substrate and associated with the source/drain feature;
a contact plug disposed on the source/drain feature and electrically coupled to the source/drain feature, wherein the contact plug is positioned closer to the first gate stack than the second gate stack; and
an air gap including a first portion disposed between the contact plug and the first gate stack, wherein the source/drain feature, the sidewall spacer and the conductive layer are exposed to the first portion of the air gap.

17. The device of claim 16 , wherein the air gap further includes a second portion disposed between the contact plug and the second gate stack, and
wherein no portion of the second gate stack is exposed to the second portion of the air gap.

18. The device of claim 17 , further comprising a nitride layer disposed directly on the contact plug, wherein the nitride layer is exposed to the first and second portions of the air gap.

19. The device of claim 17 , wherein the source/drain feature is exposed to the second portion of the air gap.

20. The device of claim 16 , further comprising:
an etch stop layer disposed directly on the first gate stack; and
an interlayer dielectric layer disposed on the etch stop layer, and
wherein the etch stop layer and the interlayer dielectric layer are exposed to the first portion of the air gap.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Lai Bo-Yu
• Yeong Sai-Hooi
• Yang Feng-Cheng
• Lin Yih-Ann
• Chen Yen-Ming

Classifications

• H10W76/60

  Seals · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title