Methods of patterning small via pitch dimensions

Patent metadata

Field	Value
Publication number	US-9099530-B2
Application number	US-201414273080-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 7, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

First claim

What is claimed is:

1. An integrated circuit method, comprising:
forming a hard mask layer on a substrate, the hard mask layer including two trench openings;
forming a patterned resist layer over the hard mask layer, wherein the patterned resist layer includes two openings aligned with the two trench openings of the hard mask layer, wherein forming the patterned resist layer over the hard mask layer includes forming the patterned resist layer using a photomask that includes two features and an optical proximity correction feature linking the two features; and
etching the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

2. The method of claim 1 , wherein the two trench openings each have an elongated shape oriented in a first direction and the two openings of the patterned resist layer are spaced away from each other in a second direction different from the first direction.

3. The method of claim 2 , wherein the second direction is orthogonal to the first direction.

4. The method of claim 2 , wherein the second direction intersects with the first direction at an angle of less than 90 degrees.

5. The method of claim 2 , further comprising forming spacers on sidewalls of the patterned resist layer and the hard mask layer by a procedure including deposition and etching prior to the etching of the substrate.

6. The method of claim 5 , wherein the spacers fill in a necking portion between the two openings of the patterned resist layer, resulting in two separate openings defined by the patterned resist layer and the spacers.

7. The method of claim 2 , further comprising:
removing the patterned resist layer after etching the substrate; and
thereafter, etching the substrate to form two trenches and two vias in the substrate.

8. The method of claim 7 , further comprising:
filling the two trenches and the two vias with a conductive material; and
planarizing the conductive material and the substrate.

9. The method of claim 1 , wherein etching the substrate includes etching an interlayer dielectric (ILD) layer.

10. An integrated circuit (IC) method, comprising:
forming a patterned resist layer having two openings on a substrate, wherein forming the patterned resist layer includes forming the patterned resist layer using a photomask that includes two features and an optical proximity correction feature linking the two features;
depositing a spacer layer on sidewalls of the two openings and in between the two openings; and
etching the substrate through the two openings using the patterned resist layer and the spacer layer as a combined etch mask.

11. The method of claim 10 , wherein the two openings of the patterned resist layer correspond to an image of the two features and the OPC feature of the photomask.

12. The method of claim 10 , wherein the substrate includes a dielectric material layer formed on a semiconductor wafer and the etching includes etching the dielectric material layer.

13. The method of claim 12 , further comprising forming, on the dielectric material layer, a hard mask having two trench openings before forming the patterned resist layer on the substrate, wherein the two openings of the patterned resist layer overlap with the two trench openings of the hard mask.

14. The method of claim 13 , further comprising:
removing the patterned resist layer;
thereafter, etching the dielectric material layer to form two trenches and two vias in the dielectric material layer;
depositing a conductive material in the two trenches and two vias; and
performing a chemical mechanical polishing (CMP) process to remove excess conductive material on the dielectric material layer.

15. The method of claim 10 , wherein depositing the spacer layer includes forming the spacer layers by a procedure including depositing a dielectric film and anisotropically etching the dielectric film.

16. An integrated circuit (IC) method, comprising:
forming a dielectric material layer on a substrate;
forming, on the dielectric material layer, a hard mask having two trench openings;
forming a patterned resist layer on the hard mask, wherein the patterned resist layer includes two openings that overlap with the two trench openings, wherein forming the patterned resist layer on the hard mask includes forming the patterned resist layer using a photomask that includes two features and an optical proximity correction (OPC) feature linking the two features; and
etching the dielectric material layer using the hard mask and the patterned resist layer as a combined etch mask.

17. The method of claim 16 , further comprising:
receiving an IC design layout for an integrated circuit with via patterns;
adding the OPC feature on the IC design layout to link the two features with the OPC feature to form a modified IC design layout; and
making the photomask using the modified IC design layout.

18. The method of claim 16 , further comprising
removing the patterned resist layer; and
thereafter, etching the dielectric material layer through the two trench openings of the hard mask, resulting in trench lines and vias in the dielectric material layer.

19. The method of claim 16 , further comprising forming a spacer layer within the two openings and the two trench openings prior to etching the dielectric material layer using the hard mask and the patterned resist layer as the combined etch mask.

20. The method of claim 16 , forming a conductive feature within the two trench openings.

Assignees

• Taiwan Semiconductor Mfg
• Taiwan Semiconductor Mfg Compnay Ltd

Inventors

• Lin Chung-Yi
• Yang Jiing-Feng
• Huang Tzu-Hao
• Hsieh Chih-Hao
• Chen Dian-Hau
• Chen Hsiang-Lin
• Kao Ko-Bin
• Cheng Yung-Shih

Classifications

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title