Metal gate stack having TaAlCN layer

Patent metadata

Field	Value
Publication number	US-9337192-B2
Application number	US-201414532228-A
Country	US
Kind code	B2
Filing date	Nov 4, 2014
Priority date	Sep 24, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a semiconductor substrate; and
a gate stack disposed over the semiconductor substrate, wherein the gate stack includes:
a gate dielectric layer disposed over the semiconductor substrate;
a multi-function blocking/wetting layer disposed in contact with the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN);
a work function layer disposed over the multi-function blocking/wetting layer; and
a conductive layer disposed over the work function layer,

wherein the multi-function blocking/wetting layer includes multiple TaAlCN layers with different nitrogen atomic concentrations,
wherein the multi-function blocking/wetting layer includes a bottom TaAlCN layer and a top TaAlCN layer, and
wherein the bottom TaAlCN layer has a higher nitrogen atomic concentration than the top TaAlCN layer.

2. The integrated circuit device of claim 1 , wherein the gate dielectric layer includes a high-k dielectric layer.

3. The integrated circuit device of claim 2 , wherein the gate dielectric layer includes an interfacial dielectric layer disposed between the high-k dielectric layer and the semiconductor substrate.

4. The integrated circuit device of claim 1 , wherein the nitrogen atomic concentration of the bottom TaAlCN layer is about 5% to about 15% and a carbon atomic concentration of the bottom TaAlCN layer is about 5% to about 20%.

5. The integrated circuit device of claim 1 , wherein the bottom TaAlCN layer has a first nitrogen atomic concentration ranging from about 5% to about 15% and the top TaAlCN layer has a second nitrogen atomic concentration ranging from about 2% to about 5%.

6. The integrated circuit device of claim 1 , wherein the multi-function blocking/wetting layer has a Ta:Al ratio of about 1:1 to about 1:3.

7. The integrated circuit device of claim 1 , wherein
the semiconductor substrate includes a fin active region; and
the gate stack is formed on the fin active region.

8. The integrated circuit device of claim 7 , further comprising source and drain (S/D) features, wherein the semiconductor substrate is a silicon substrate and the S/D features includes a semiconductor material different from the semiconductor substrate for strain effect.

9. An integrated circuit device comprising
a semiconductor substrate having a first region for a n-channel field effect transistor and a second region for a p-channel channel field effect transistor;
a first gate stack disposed over the semiconductor substrate within the first region, wherein the first gate stack includes a high-k dielectric layer disposed over the semiconductor substrate, a first tantalum aluminum carbon nitride (TaAlCN) layer disposed over the high-k dielectric layer, and an n work function (nWF) metal layer with a first work function disposed directly on the first TaAlCN layer; and
a second gate stack disposed over the semiconductor substrate within the second region, wherein the second gate stack includes the high-k dielectric layer disposed over the semiconductor substrate, the first TaAlCN layer disposed over the high-k dielectric laver, and a p work function (pWF) metal layer with a second work function disposed directly on the first TaAlCN layer, the second work function being greater than the first work function,
wherein the nWF metal layer includes a second TaAlCN layer having a nitrogen concentration less than that of the first TaAlCN layer.

10. The integrated circuit device of claim 9 , wherein
the pWF metal layer is a layer of a second metal selected from the group consisting of titanium nitride (TiN), ruthenium (Ru), molybdenum (Mo), platinum (Pt), iridium (Ir), platinum silicon (PtSi), and molybdenum nitride (MoN).

11. The integrated circuit device of claim 9 , further comprising:
an aluminum layer disposed directly on the nWF metal layer within the first region and on the pWF metal layer within the second region; and
a capping layer disposed between the high-k dielectric layer and the first TaAlCN layer, wherein the capping layer includes one of titanium nitride, tantalum nitride and a combination thereof.

12. The integrated circuit device of claim 9 , wherein
the semiconductor substrate includes a fin active region; and
the first and second gate stacks are disposed over the fin active region.

13. The integrated circuit device of claim 9 , wherein the first TaAlCN layer has a nitrogen atomic concentration of about 5% to about 15% and a carbon atomic concentration of about 5% to about 20%, and a Ta:Al ratio of about 1:1 to about 1:3.

14. An integrated circuit device comprising:
a substrate having at least two source/drain regions disposed therein; and
a gate stack disposed on the substrate between the at least two source/drain regions, the gate stack including:
a dielectric layer disposed on the substrate;
a blocking layer disposed on the substrate and within the dielectric layer, wherein the blocking layer includes a bottom TaAlCN layer and a top TaAlCN layer, and wherein the bottom TaAlCN layer has a higher nitrogen atomic concentration than the top TaAlCN layer; and
a work function layer disposed on the substrate and within the blocking layer, wherein the work function layer has a different composition than the blocking layer.

15. The integrated circuit device of claim 14 ,
wherein the work function layer includes TaAlCN, and
wherein the work function layer has a nitrogen concentration that is different than the nitrogen atomic concentration of the bottom TaAlCN layer of the blocking layer.

16. The integrated circuit device of claim 14 , wherein the bottom TaAlCN layer has a first nitrogen atomic concentration between about 5% and about 15% and the top TaAlCN layer has a second nitrogen atomic concentration between about 2% and about 5%.

17. The integrated circuit device of claim 14 , wherein the dielectric layer extends to a topmost surface of the gate stack and has a recess defined therein, and wherein the blocking layer and the work function layer are disposed within the recess.

18. The integrated circuit device of claim 14 , wherein the blocking layer physically contacts a horizontal surface and opposing vertical side surfaces of the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Jangjian Shiu-Ko
• Wang Ting-Chun
• Jeng Chi-Cherng
• Liu Chi-Wen

Classifications

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title