Die sidewall coatings and related methods

Patent metadata

Field	Value
Publication number	US-12374555-B2
Application number	US-202418742204-A
Country	US
Kind code	B2
Filing date	Jun 13, 2024
Priority date	Aug 17, 2017
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

First claim

What is claimed is:

1. A method of forming a semiconductor package, the method comprising:
forming a plurality of notches into a first side of a semiconductor substrate;
applying a coating material into the plurality of notches;
after applying the coating material, forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; and
singulating the semiconductor substrate through the coating material into a plurality of semiconductor packages;
wherein the coating material comprises a thickness equal to a depth of the plurality of notches extending from the first side of the semiconductor substrate to a bottom of the plurality of notches.

2. The method of claim 1 , further comprising applying one of a second organic material or a backmetal over a second side of the semiconductor substrate opposite the first side of the semiconductor substrate.

3. The method of claim 1 , wherein a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

4. The method of claim 1 , wherein only a plurality of sidewalls of the semiconductor substrate after singulation are directly coupled to the coating material.

5. The method of claim 1 , further comprising singulating the semiconductor substrate through the first organic material.

6. The method of claim 1 , wherein the first organic material comprises a die support structure that comprises two or more layers.

7. A method of forming a semiconductor package, the method comprising:
forming a plurality of notches into a first side of a semiconductor substrate;
applying a coating material into the plurality of notches;
after applying the coating material, forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; and
singulating the semiconductor substrate through the coating material and the first organic material into a plurality of semiconductor packages;
wherein a thickness of the coating material of a semiconductor package of the plurality of semiconductor packages is equal to a thickness of a die of the semiconductor package.

8. The method of claim 7 further comprising applying one of a second organic material or a backmetal over a second side of the semiconductor substrate opposite the first side of the semiconductor substrate.

9. The method of claim 7 , a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

10. The method of claim 7 , wherein forming a first organic material over the first side of the semiconductor substrate further comprises forming a permanent die support structure comprising a perimeter comprising a closed shape.

11. The method of claim 10 , further comprising forming one of a second permanent die support structure or a temporary die support structure coupled to a second side of the semiconductor substrate.

12. The method of claim 10 , wherein the permanent die support structure comprises two or more layers.

13. The method of claim 7 , further comprising forming a second plurality of notches within the plurality of notches, wherein a width of the second plurality of notches is less than a width of the plurality of notches.

14. A method of forming a semiconductor package, the method comprising:
forming a plurality of notches into a first side of a semiconductor substrate;
applying a coating material into the plurality of notches;
after applying the coating material, forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; and
singulating the semiconductor substrate through the coating material and the first organic material into a plurality of semiconductor packages;
wherein the coating material comprises a thickness equal to a depth of the plurality of notches extending from the first side of the semiconductor substrate to a bottom of the plurality of notches; and
wherein the plurality of semiconductor packages comprises a plurality of die, each die of the plurality of die comprising stepped sidewalls.

15. The method of claim 14 , further comprising applying one of a second organic material or a backmetal over the second side of the semiconductor substrate.

16. The method of claim 14 , wherein a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

17. The method of claim 14 , wherein forming a first organic material over the first side of the semiconductor substrate further comprises forming a permanent die support structure comprising a perimeter comprising a closed shape.

18. The method of claim 17 , further comprising forming one of a second permanent die support structure or a temporary die support structure coupled to the second side of the semiconductor substrate.

19. The method of claim 17 , wherein the permanent die support structure comprises two or more layers.

20. The method of claim 14 , wherein the first organic material is directly coupled to the first side of the semiconductor substrate.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Carney Francis J
• Lin Yusheng
• Seddon Michael J
• Chew Chee Hiong
• Wang Soon Wei
• Kurose Eiji

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title