Semiconductor packages with die including cavities and related methods

Patent metadata

Field	Value
Publication number	US-12374554-B2
Application number	US-202418416760-A
Country	US
Kind code	B2
Filing date	Jan 18, 2024
Priority date	Sep 17, 2015
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side opposite the first side;
a cavity extending into the second side of the semiconductor die;
a plurality of notches extending into the first side of the semiconductor die;
a backmetal coupled within the cavity; and
an organic material coupled over the first side of the semiconductor die and within the plurality of notches;
wherein the plurality of notches form a step around an outermost perimeter of the first side; and
wherein a greatest depth of the cavity extends only partially into the second side of the semiconductor die.

2. The semiconductor package of claim 1 , wherein the organic material only partially covers one or more sidewalls of the semiconductor die.

3. The semiconductor package of claim 1 , wherein the organic material further comprises a die support structure.

4. The semiconductor package of claim 1 , wherein a largest planar surface of the second side of the semiconductor die is within the cavity.

5. The semiconductor package of claim 1 , further comprising a conductive material coupled within the cavity and directly coupled to only a largest planar surface of the backmetal.

6. The semiconductor package of claim 5 , wherein multiple surfaces of the backmetal are exposed on multiple outer surfaces of the semiconductor package.

7. The semiconductor package of claim 1 , wherein the backmetal covers an entirety of the second side of the semiconductor die.

8. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side opposite the first side, the first side comprising a step along an outer perimeter of the first side;
a cavity extending into the second side of the semiconductor die;
a backmetal coupled within the cavity; and
an organic material coupled over the first side of the semiconductor die and within the step;
wherein a greatest depth of the cavity extends only partially into the second side of the semiconductor die.

9. The semiconductor package of claim 8 , wherein the organic material only partially covers one or more sidewalls of the semiconductor die.

10. The semiconductor package of claim 8 , wherein the organic material further comprises a die support structure.

11. The semiconductor package of claim 8 , wherein a largest planar surface of the second side of the semiconductor die is within the cavity.

12. The semiconductor package of claim 8 , further comprising a conductive material coupled within the cavity and directly coupled to only a largest planar surface of the backmetal.

13. The semiconductor package of claim 8 , wherein the backmetal covers an entirety of the second side of the semiconductor die.

14. The semiconductor package of claim 8 , wherein a thinned portion of the semiconductor die is less than five microns thick.

15. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side opposite the first side;
a cavity extending into the second side of the semiconductor die;
a backmetal coupled within the cavity; and
an organic material coupled over the first side of the semiconductor die, wherein the organic material only partially covers one or more sidewalls of the semiconductor die;
wherein a greatest depth of the cavity extends only partially into the second side of the semiconductor die.

16. The semiconductor package of claim 15 , wherein the organic material further comprises a die support structure.

17. The semiconductor package of claim 15 , wherein a largest planar surface of the second side of the semiconductor die is within the cavity.

18. The semiconductor package of claim 15 , further comprising a conductive material coupled within the cavity and directly coupled to only a largest planar surface of the backmetal.

19. The semiconductor package of claim 18 , wherein multiple surfaces of the backmetal are exposed on multiple outer surfaces of the semiconductor package.

20. The semiconductor package of claim 15 , wherein a thinned portion of the semiconductor die is less than five microns thick.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J
• Chew Chee Hiong
• Wang Soon Wei
• Kurose Eiji

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W74/016

  using moulds · CPC title