Verification of hardware design for data transformation component

Patent metadata

Field	Value
Publication number	US-12373621-B2
Application number	US-202418675048-A
Country	US
Kind code	B2
Filing date	May 27, 2024
Priority date	Oct 8, 2019
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

First claim

What is claimed is:

1. A computer-implemented method of verifying a hardware design for a main component, the main component being representable as a hierarchical set of components, the hierarchical set of components comprising (i) a plurality of leaf components which do not have children in the hierarchical set of components, and (ii) one or more parent components which each comprise one or more leaf components in the hierarchical set of components, wherein the hardware design for the main component comprises a hardware design for each component of the hierarchical set of components, the method comprising:
for each of the plurality of leaf components, verifying, at one or more processors, that an instantiation of the hardware design for the leaf component generates an expected output transaction in response to each of a plurality of test input transactions; and
for each of the one or more parent components, formally verifying, at the one or more processors using a formal verification tool, that an instantiation of an abstracted hardware design for the parent component generates an expected output transaction in response to each of a plurality of test input transactions, wherein, in the abstracted hardware design for the parent component, logic for driving an output of each of the at least one leaf components has been replaced with a corresponding abstracted component that is configured to, for a specific input transaction to the leaf component, produce a specific output transaction with a causal deterministic relationship to the specific input transaction, wherein during formal verification the formal verification tool is configured to select the specific input transaction and the specific output transaction pair to be each possible valid input transaction and valid output transaction pair for the leaf component.

2. The method of claim 1 , wherein the corresponding abstracted component for a leaf component is defined in a formal verification language by a definition of a symbolic input transaction to the leaf component which specifies the specific input transaction, a definition of a symbolic output transaction of the leaf component which specifies the specific output transaction, and one or more constraints that establish a deterministic causal relationship between the symbolic input transaction and the symbolic output transaction.

3. The method of claim 2 , wherein the symbolic input transaction to the leaf component is a symbolic constant that represents the valid input transactions to the leaf component.

4. The method of claim 2 , wherein the symbolic output transaction to the leaf component is a symbolic constant that represents the valid output transactions for the leaf component.

5. The method of claim 2 , wherein the one or more constraints are implemented by one or more formal assumption statements.

6. The method of claim 2 , wherein when a parent component comprises a plurality of leaf components the abstracted hardware design for that parent component comprises a description of a relationship between the symbolic input and output transactions of the plurality of leaf components.

7. The method of claim 1 , wherein each component of the hierarchical set of components is configured to receive one or more data inputs, perform a data transformation on the one or more data inputs, and output a result of the data transformation.

8. The method of claim 1 , wherein verifying that an instantiation of the hardware design for a leaf component generates an expected output transaction in response to an input transaction comprises verifying that the instantiation of the hardware design for the leaf component generates an output transaction, with a deterministic causal relationship to the input transaction, that is correct with respect to a data transformation to be performed by the leaf component.

9. The method of claim 1 , wherein verifying that an instantiation of the abstracted hardware design for a parent component generates an expected output transaction in response to an input transaction comprises verifying that an instantiation of the abstracted hardware design for the parent component generates an output transaction, with a deterministic causal relationship to the input transaction, that has been generated by processing the input transaction through an expected combination of the one or more leaf components of that parent component.

10. The method of claim 1 , wherein the plurality of test input transactions for a leaf component comprises all valid input transactions to the leaf component.

11. The method of claim 1 , wherein the plurality of test input transactions for a parent component comprises all valid input transactions to the parent component.

12. The method of claim 1 , wherein verifying that an instantiation of the hardware design for a leaf component generates an expected output transaction in response to each of a plurality of test input transactions comprises formally verifying, using a formal verification tool, that an instantiation of the hardware design for the leaf component generates an expected output transaction in response to each of the plurality of test input transactions.

13. The method of claim 1 , wherein the hierarchical set of components further comprises at least one grandparent component, wherein the at least one grandparent component comprises at least one parent component in the hierarchical set of components.

14. The method of claim 1 , further comprising, in response to determining that at least one of the verifications was not successful, determining whether the at least one of the verifications that was not successful was inconclusive; and in response to determining that the at least one of the verifications that was not successful was inconclusive, representing the main component using a different hierarchical set of data transformation components, and repeating the verifications for at least a portion of the components of the different hierarchical set of components.

15. The method of claim 14 , further comprising, in response to determining that the verification of the hardware design for a leaf component was inconclusive, converting that leaf component into a parent component that comprises a plurality of leaf components to form the different hierarchical set of components, and verifying the hardware design for each of the plurality of leaf components of that parent component and verifying an abstracted hardware design for that parent component.

16. The method of claim 1 , wherein the main component, the one or more parent components and the plurality of leaf components are data transformation components.

17. The method of claim 1 , further comprising, in response to determining that the verifications were successful, manufacturing, using an integrated circuit manufacturing system, an integrated circuit embodying the main component according to the hardware design.

18. The method of claim 1 , wherein, when processed at an integrated circuit manufacturing system, the hardware design for the main component configures the integrated circuit manufacturing system to manufacture an integrated circuit embodying the main component.

19. A system for verifying a hardware design for a main component, the main component being representable as a hierarchical set of components, the hierarchical set of components comprising (i) a plurality of leaf components which do not have children in the hierarchical set of components, and (ii) one or more parent components which each comprise one or more leaf components in the hierarchical se

Assignees

• Imagination Tech Ltd

Inventors

• Elliott Sam

Classifications

• G01R31/318314

  Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261) · CPC title

• G06F30/3308

  using simulation · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title