Verification of hardware design for data transformation component

Patent metadata

Field	Value
Publication number	US-11074381-B2
Application number	US-202017065678-A
Country	US
Kind code	B2
Filing date	Oct 8, 2020
Priority date	Oct 8, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

First claim

What is claimed is:

1. A computer-implemented method of verifying a hardware design for a main data transformation component, the main data transformation component being representable as a hierarchical set of data transformation components, the hierarchical set of data transformation components comprising (i) a plurality of leaf data transformation components which do not have children in the hierarchical set of data transformation components, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components in the hierarchical set of data transformation components, wherein the hardware design for the main data transformation component comprises a hardware design for each data transformation component of the hierarchical set of data transformation components, the method comprising:
for each of the plurality of leaf data transformation components, verifying, at one or more processors, that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions; and
for each of the one or more parent data transformation components, formally verifying, at the one or more processors using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions, wherein the abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that is configured to, for a specific input transaction to the child data transformation component, produce a specific output transaction with a causal deterministic relationship to the specific input transaction, wherein during formal verification the formal verification tool is configured to select the specific input transaction and the specific output transaction pair to be each possible valid input transaction and valid output transaction pair for the child data transformation component;
wherein an instantiation of a hardware design embodies that hardware design in a form which can be tested to verify that hardware design.

2. The method of claim 1 , wherein the corresponding abstracted component for a child data transformation component is defined in a formal verification language by a definition of a symbolic input transaction to the child data transformation component which specifies the specific input transaction, a definition of a symbolic output transaction of the child data transformation component which specifies the specific output transaction, and one or more constraints that establish a deterministic causal relationship between the symbolic input transaction and the symbolic output transaction.

3. The method of claim 2 , wherein the symbolic input transaction to the child data transformation component is a symbolic constant that represents the valid input transactions to the child data transformation component.

4. The method of claim 2 , wherein the symbolic output transaction to the child data transformation component is a symbolic constant that represents the valid output transactions for the child data transformation component.

5. The method of claim 2 , wherein the one or more constraints are implemented by one or more formal assumption statements.

6. The method of claim 2 , wherein when a parent data transformation component comprises a plurality of child data transformation components the abstracted hardware design for that parent data transformation component comprises a description of a relationship between the symbolic input and output transactions of the plurality of child data transformation components.

7. The method of claim 1 , wherein each data transformation component of the hierarchical set of data transformation components is configured to receive one or more data inputs, perform a data transformation on the one or more data inputs, and output a result of the data transformation.

8. The method of claim 1 , wherein verifying that an instantiation of the hardware design for a leaf data transformation component generates an expected output transaction in response to an input transaction comprises verifying that the instantiation of the hardware design for the leaf data transformation component generates an output transaction, with a deterministic causal relationship to the input transaction, that is correct with respect to a data transformation to be performed by the leaf data transformation component.

9. The method of claim 1 , wherein verifying that an instantiation of the abstracted hardware design for a parent data transformation component generates an expected output transaction in response to an input transaction comprises verifying that an instantiation of the abstracted hardware design for the parent data transformation component generates an output transaction, with a deterministic causal relationship to the input transaction, that has been generated by processing the input transaction through an expected combination of the one or more child data transformation components of that parent data transformation component.

10. The method of claim 1 , wherein the plurality of test input transactions for a leaf data transformation component comprises all valid input transactions to the leaf data transformation component.

11. The method of claim 1 , wherein the plurality of test input transactions for a parent data transformation component comprises all valid input transactions to the parent data transformation component.

12. The method of claim 1 , wherein verifying that an instantiation of the hardware design for a leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions comprises formally verifying, using a formal verification tool, that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of the plurality of test input transactions.

13. The method of claim 1 , further comprising outputting one or more control signals indicating whether each of the verifications was successful.

14. The method of claim 1 , further comprising, in response to determining that at least one of the verifications was not successful, determining whether the at least one of the verifications that was not successful was inconclusive; and in response to determining that the at least one of the verifications that was not successful was inconclusive, representing the main data transformation component using a different hierarchical set of data transformation components, and repeating the verifications for at least a portion of the data transformation components of the different hierarchical set of data transformation components.

15. The method of claim 14 , further comprising, in response to determining that the verification of the hardware design for a leaf data transformation component was inconclusive, converting that leaf data transformation component into a parent data transformation component that comprises a plurality of leaf data transformation components to form the different hierarchical set of data transformation components, and verifying the hardware design for each of the plurality of child data transformation components of that parent data transformation component and verifying an abstracted hardware design for that parent data transform

Assignees

• Imagination Tech Ltd

Inventors

• Elliott Sam

Classifications

• G06F2115/02

  System on chip [SoC] design · CPC title

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G01R31/318314

  Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261) · CPC title