Image sensor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12364047-B2
Application number	US-202217721914-A
Country	US
Kind code	B2
Filing date	Apr 15, 2022
Priority date	Jun 3, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Provided is an image sensor including a first layer including a first semiconductor substrate including a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate, a second layer including a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction, a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer, a third layer including a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction, and a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.

First claim

What is claimed is:

1. An image sensor, comprising:
a first layer comprising a first semiconductor substrate comprising a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate;
a second layer comprising a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction;
a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer;
a third layer comprising a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction; and
a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.

2. The image sensor of claim 1 , wherein a transfer transistor is provided on the first semiconductor substrate, and transistors included in a pixel circuit separate from the transfer transistor are provided on the second semiconductor substrate.

3. The image sensor of claim 1 , wherein transistors included in a pixel circuit comprising a transfer transistor, a reset transistor, and a drive transistor are provided on the first semiconductor substrate.

4. The image sensor of claim 1 , wherein an extended length of the first bonding metal is different from an extended length of the second bonding metal in a second direction perpendicular to the first direction.

5. The image sensor of claim 1 , wherein extended lengths of the first bonding metal and the second bonding metal included in at least one of the plurality of first bonding structures in a second direction perpendicular to the first direction are different from extended lengths of the first bonding metal and the second bonding metal included in the other of the plurality of first bonding structures in the second direction.

6. The image sensor of claim 1 , wherein an extended length of the third bonding metal included in at least one of the plurality of second bonding structures is different from an extended length of the third bonding metal included in the other of the plurality of second bonding structures in a second direction perpendicular to the first direction.

7. The image sensor of claim 1 , wherein a thickness of the second semiconductor substrate is equal to or greater than 10 nm and equal to or less than 2 μm in the first direction.

8. The image sensor of claim 1 , wherein a lowermost wiring of the second wiring layer includes tungsten (W) or copper (Cu).

9. The image sensor of claim 1 , wherein the first layer, the second layer, and the third layer are bonded to each other by a copper-copper (Cu—Cu) bonding method.

10. An image sensor, comprising:
a first layer comprising a first semiconductor substrate comprising a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate;
a second layer comprising a second semiconductor substrate and a second wiring layer provided on the second semiconductor substrate, and bonded to the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction; and
a third layer comprising a third semiconductor substrate and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer based on a third bonding metal exposed to one surface of the third wiring layer being in contact with a bonding via penetrating the second semiconductor substrate in the first direction,
wherein the bonding via comprises an upper via region in contact with a second wiring included in the second wiring layer and having a first width in a second direction perpendicular to the first direction, and a lower via region in contact with the third bonding metal and having a second width greater than the first width in the second direction, and
wherein a first spacer layer is provided between the second semiconductor substrate and the bonding via.

11. The image sensor of claim 10 , wherein a second spacer layer is provided between the second semiconductor substrate and the third wiring layer, and
wherein a thickness of the upper via region is greater than a thickness of the second spacer layer in the first direction.

12. The image sensor of claim 11 , wherein the thickness of the upper via region is between 100 nm and 800 nm.

13. The image sensor of claim 11 , wherein a material of the first spacer layer is different from a material of the second spacer layer.

14. The image sensor of claim 11 , wherein the first spacer layer is a composite film comprising silicon carbonitride (SiCN).

15. The image sensor of claim 11 , wherein the second spacer layer is a composite film comprising metal oxide.

16. An image sensor, comprising:
a first layer, a second layer, and a third layer bonded to each other in that order in a first direction, each of the first layer, the second layer, and the third layer comprising a semiconductor substrate and a wiring layer provided on the semiconductor substrate in the first direction, and divided into a plurality of regions in a second direction and a third direction perpendicular to the first direction,
wherein the plurality of regions comprise:
a first region in which the first layer comprises a first semiconductor substrate in which a pixel unit is provided, and the second layer comprises a second semiconductor substrate;
a second region in which the first layer is bonded to the second layer by a first bonding structure, and the second layer is bonded to the third layer by a second bonding structure; and
a third region comprises at least one of a first through-silicon via extending from a surface exposed to the first semiconductor substrate and connected to a first wiring included in a first wiring layer included in the first layer, and a second through-silicon via extending from a surface exposed to a third semiconductor substrate included in the third layer and connected to a third wiring included in a third wiring layer included in the third layer.

17. The image sensor of claim 16 , wherein the plurality of regions further comprises a fourth region comprising the first bonding structure and the second bonding structure, and being provided adjacent to the first region, the second region, and the third region.

18. The image sensor of claim 16 , wherein the first region comprises the first bonding structure, and
wherein the third region comprises the first bonding structure and the second bonding structure.

19. The image sensor of claim 18 , wherein, in the third region, the first bonding structure and the second bonding structure are provided to overlap with each other in the first direction.

20. The image sensor of claim 18 , wherein the first bonding structure and the second bonding structure are provided

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Doowon
• Moon Changrok
• Lim Kyungtae

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title