Memory device with reduced area

Patent metadata

Field	Value
Publication number	US-12362017-B2
Application number	US-202418632856-A
Country	US
Kind code	B2
Filing date	Apr 11, 2024
Priority date	May 24, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of word lines (WLs) above a substrate;
a plurality of memory strings laterally isolated from each other, wherein each of the plurality of memory strings is operatively coupled to a respective subset of the plurality of WLs; and
a plurality of drivers each configured to control a corresponding one of the plurality of WLs and comprising a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

2. The memory device of claim 1 , wherein the first transistor of a first one of the drivers is formed in a first well of the substrate, and the second transistor of the first driver is formed in a second well of the substrate.

3. The memory device of claim 2 , wherein the first well is spaced apart from the second well.

4. The memory device of claim 2 , wherein the first well has the second conductive type and the second well has the first conductive type.

5. The memory device of claim 2 , wherein the first transistor of a second one of the plurality of drivers is disposed immediately next to the first transistor of the first driver, and the second transistor of the second driver is disposed immediately next to the second transistor of the first driver, and wherein the WLs controlled by the first driver and the second driver, respectively, are disposed in a same memory layer.

6. The memory device of claim 5 , wherein the first transistor of the second driver is also disposed in the first well, and the second transistor of the second driver is also disposed in the second well.

7. The memory device of claim 2 , wherein the first transistor of a third one of the plurality of drivers is disposed immediately next to the first transistor of the first driver, and the second transistor of the third driver is disposed immediately next to the second transistor of the first driver, and wherein the WLs controlled by the first driver and third driver, respectively, are disposed in neighboring memory layers.

8. The memory device of claim 7 , wherein the first transistor of the third driver is also disposed in the first well, and the second transistor of the third driver is also disposed in the second well.

9. The memory device of claim 1 , wherein the plurality of drivers interposed between the plurality of WLs and the substrate.

10. The memory device of claim 2 , wherein the subset of WLs are vertically spaced apart and electrically isolated from one another, and wherein the subset of the plurality of WLs form a staircase profile.

11. The memory device of claim 1 , further comprising a plurality of memory strings laterally isolated from each other, wherein each of the plurality of memory strings is operatively coupled to a respective subset of the plurality of WLs.

12. A memory device, comprising:
a memory array comprising a plurality of word lines (WLs) over a substrate, the plurality of WLs each extending along a first lateral direction; and
a plurality of WL drivers operatively coupled to the plurality of WLs, respectively, wherein each of the plurality of WL drivers comprises at least a corresponding one of a plurality of first transistors having a first conductive type and a corresponding one of a plurality of second transistors having a second conductive type opposite to the first conductive type;
wherein the plurality of WLs comprise a first subset of WLs that are disposed in different memory layers along a vertical direction and have respectively different lengths extending along the first lateral direction.

13. The memory device of claim 12 , wherein the first transistors, operatively coupled to the first subset of WLs, are disposed in a first region of a substrate, and the second transistors, operatively coupled to the first subset of WLs, are disposed in a second region of the substrate; and wherein the first region and the second region are spaced apart from each other.

14. The memory device of claim 13 , wherein the first region and the second region are positioned on opposite sides of the memory array along the first lateral direction.

15. The memory device of claim 13 , wherein the first region is a first well having the second conductive type, and the second region is a second well having the first conductive type.

16. The memory device of claim 12 , wherein the plurality of WL drivers are disposed between the substrate and the memory array.

17. The memory device of claim 12 , wherein the plurality of WLs comprise a second subset of WLs that are disposed in a same memory layer along the vertical direction and have a same length extending along the first lateral direction.

18. A method of forming a memory device, comprising:
forming a first transistor in a first region of a substrate, wherein the first transistor has a first conductive type;
forming a second transistor in a second region of the substrate spaced apart from the first region, wherein the second transistor has a second conductive type opposite to the first conductive type;
forming a memory array over the first and second transistors, wherein the memory array includes a plurality of word lines (WLs) each operatively coupled to a corresponding subset of memory cells of the memory array;
coupling both the first transistor and second transistor to a first one of the plurality of WLs;
forming a third transistor in the first region immediately next to the first transistor, wherein the third transistor has the first conductive type;
forming a fourth transistor in the second region immediately next to the second transistor, wherein the fourth transistor has the second conductive type; and
coupling both the third transistor and fourth transistor to a second one of the plurality of WLs.

19. The method of claim 18 , wherein the first WL and second WL are disposed in a same memory layer.

20. The method of claim 19 , further comprising:
forming a plurality of drivers, wherein each of the plurality of drivers is configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chun-Ying
• Huang Chia-En
• Lee Chieh

Classifications

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title