Three dimensional stacked nonvolatile semiconductor memory

Patent metadata

Field	Value
Publication number	US-2015115350-A1
Application number	US-201514589523-A
Country	US
Kind code	A1
Filing date	Jan 5, 2015
Priority date	Apr 23, 2008
Publication date	Apr 30, 2015
Grant date	—

Abstract

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.

First claim

What is claimed is:

1 . A three dimensional stacked nonvolatile semiconductor memory comprising:
a semiconductor substrate; a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction, wherein each of the first and second blocks is comprised of at least two conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least two conductive layers by being insulated therefrom, and columnar semiconductors having lower ends connected to the semiconductor substrate and upper ends connected to the bit line and passing through the at least two conductive layers, wherein the at least two conductive layers are a select gate line or a word line, a select gate transistor is comprised of the select gate line and the columnar semiconductor, and a memory cell is comprised of the word line and the columnar semiconductor, and wherein a source diffusion layer, which is common to the first and second blocks, is disposed in the semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above the at least two conductive layers, is interposed between the first and second blocks.

2 . The memory according to claim 1 , wherein the contact plug is comprised of a columnar semiconductor having the same structure as those of the columnar semiconductors.

3 . The memory according to claim 1 , further comprising a dummy bit line and a connection member disposed alongside the bit line, wherein the source line is disposed above the bit line as well as connected to the upper end of the contact plug through the connection member, and the dummy bit line is placed in a floating state.

4 . The memory according to claim 1 , wherein the source line is disposed alongside the bit line, and the bit line and the source line extend in the first direction together.

5 . The memory according to claim 1 , wherein the source line is connected to a common source line disposed above the bit line and the source line.

6 . The memory according to claim 1 , wherein one end in the second direction of the at least two conductive layers is formed stepwise.

7 . The memory according to claim 6 , wherein one end in the second direction of each of the at least two conductive layers is connected to an interconnect line located above the at least two conductive layers through a contact plug.

8 . The memory according to claim 7 , wherein the interconnect line is connected to the first driver.

9 . The memory according to claim 6 , wherein one end in the second direction of each of the at least two conductive layers excluding the uppermost layer is connected to an interconnect line located above the at least two conductive layers through a contact plug.

10 . The memory according to claim 9 , wherein the interconnect line is connected to the first driver.

11 . The memory according to claim 9 , wherein the other end in the second direction of the uppermost layer of the at least two conductive layers is connected to an interconnect line located above the at least two conductive layers through a contact plug.

12 . The memory according to claim 1 , wherein the memory cell and the select gate transistor comprise a NAND cell unit.

13 . The memory according to claim 1 , wherein the semiconductor substrate has a source diffusion layer, and the columnar semiconductors are connected to the source diffusion layer.

14 . The memory according to claim 13 , wherein the source diffusion layer is common to the first and second blocks.

15 . A three dimensional stacked nonvolatile semiconductor memory comprising:
a semiconductor substrate; a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction, wherein each of the first and second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least three conductive layers by being insulated therefrom, and columnar semiconductors having lower ends connected to the semiconductor substrate and upper ends connected to the bit line and passing through the at least three conductive layers, wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, and remaining conductive layers excluding the uppermost layer of the at least three conductive layers have a plate shape whose width in the first direction is larger than the width in the first direction of the first select gate lines, wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively and memory cells are comprised of the word line and the columnar semiconductors, respectively, and wherein a source diffusion layer, which is common to the first and second blocks, is disposed in the semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above the at least three conductive layers, is interposed between the first and second blocks.

16 . The memory according to claim 15 , wherein the contact plug is comprised of a columnar semiconductor which has the same structure as the columnar semiconductors passing through the at least three conductive layers.

17 . The memory according to claim 15 , wherein the source line is connected to a common source line which is provided above the bit line and the source line.

18 . The memory according to claim 15 , wherein the memory cell and the select gate transistor comprise a NAND cell unit.

19 . The memory according to claim 15 , wherein the semiconductor substrate has a source diffusion layer, and the columnar semiconductors are connected to the source diffusion layer.

20 . A three dimensional stacked nonvolatile semiconductor memory comprising:
a semiconductor substrate; and a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction, wherein each of the first and second blocks is comprised of at least two conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least two conductive layers by being insulated therefrom, and columnar semiconductors having lower ends connected to the semiconductor substrate and upper ends connected to the bit line and passing through the at least two conductive layers, wherein the at least two conductive layers are a select gate line or a word line, a select gate transistor is comprised of the select gate line and the columnar semiconductor, and a memory cell is comprised of the word line and the columnar semiconductor, and wherein the memory cell and the select gate transistor comprise a NAND c

Assignees

• Toshiba Kk

Inventors

• Maejima Hiroshi

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H01L23/535

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic