Semiconductor devices and data storage systems including the same

Patent metadata

Field	Value
Publication number	US-12355003-B2
Application number	US-202217582387-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Apr 16, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first structure including a substrate, circuit devices on the substrate, first pad layers on the circuit devices, and a second pad layer on the circuit devices; and
a second structure on the first structure,
wherein the second structure comprises,
first conductive layer including first openings on corresponding ones of the first pad layers, respectively, and a second opening on the second pad layer, the first conductive layer having a first region and a second region,
a stack structure including gate electrodes spaced apart from each other on the first region and the second region, the gate electrodes stacked on the first conductive layer in a vertical direction and extending in a first direction perpendicular to the vertical direction,
channel structures penetrating through the stack structure on the first region, each of the channel structures including a channel layer,
separation regions penetrating through the stack structure on the first region and the second region and extending in the first direction,
gate contact plugs penetrating through the stack structure, the gate contact plugs connected to the gate electrodes, respectively, and the gate contact plugs connected to the first pad layers through the first openings of the first conductive layer, respectively,
a source connection conductive layer being in contact with a lower surface of the first conductive layer, and the source connection conductive layer having a hole between the second opening of the first conductive layer and the second pad layer,
a source contact plug spaced apart from the stack structure, the source contact plug extending into the hole of the source connection conductive layer through the second opening of the first conductive layer, and the source contact plug connected to the second pad layer and the source connection conductive layer, and
a through-insulating layer in the second opening of the first conductive layer and surrounding a side surface of the source contact plug while extending partially into the hole of the source connection conductive layer.

2. The semiconductor device of claim 1 , wherein the source contact plug is spaced apart from the first conductive layer by the through-insulating layer and is electrically connected to the first conductive layer through the second pad layer and the source connection conductive layer.

3. The semiconductor device of claim 1 , wherein
the source contact plug includes a first plug portion below the first conductive layer and a second plug portion on the first plug portion, and
a first width of the first plug portion is greater than a second width of the second plug portion.

4. The semiconductor device of claim 3 , wherein
the first plug portion is in direct contact with the source connection conductive layer, and
the second plug portion is spaced apart from the source connection conductive layer in a horizontal direction.

5. The semiconductor device of claim 1 , wherein
each of the first conductive layer and the source connection conductive layer includes a semiconductor material, and
each of the second pad layer and the source contact plug includes at least one of metal and metal nitride.

6. The semiconductor device of claim 1 , wherein
the source contact plug includes a conductive plug and a conductive liner covering a side surface and a lower surface of the conductive plug, and
the conductive liner includes a vertical portion and a bent portion, the vertical portion extending downwardly through the first conductive layer in the vertical direction, the bent portion bent toward the source connection conductive layer from the vertical portion.

7. The semiconductor device of claim 1 , wherein
each of the gate contact plugs includes a first gate plug portion and a second gate plug portion on the first gate plug portion and below the first openings, and
a third width of the first gate plug portion is greater than a fourth width of the second gate plug portion.

8. The semiconductor device of claim 7 , wherein
each of the gate electrodes includes a pad region having an upper surface, the upper surface including a portion exposed upwardly in the second region,
each of the gate contact plugs includes a vertical extension portion and a horizontal extension portion, the vertical extension portion extending from the second gate plug portion in the vertical direction, the horizontal extension portion horizontally extending from the vertical extension portion and in contact with the pad region, and
the stack structure further includes buffer insulating patterns below the horizontal extension portion and insulating the gate electrodes and the vertical extension portion from each other.

9. A semiconductor device comprising:
a first structure including a substrate, circuit devices on the substrate, and first pad layers on the circuit devices, and a second pad layer on the circuit devices; and
a second structure on the first structure,
wherein the second structure comprises,
a first conductive layer including first openings on corresponding ones of the first pad layers, respectively, and a second opening on the second pad layer, the first conductive layer having a first region and a second region,
gate electrodes spaced apart from each other and stacked on the first conductive layer in a vertical direction and extending in a first direction perpendicular to the vertical direction, each of the gate electrodes including a pad region having an upper surface, the upper surface including a portion exposed upwardly in the second region,
channel structures penetrating through the gate electrodes on the first region, each of the channel structures extending in the vertical direction and including a channel layer,
gate contact plugs electrically connected to the gate electrodes, respectively, through the pad region of each of the gate electrodes, the gate contact plugs extending in the vertical direction to pass through corresponding ones of the first openings of the first conductive layer, respectively, and connected to corresponding ones of the first pad layers, respectively,
a source contact plug spaced apart from the gate electrodes, extending in the vertical direction to pass through the second opening of the first conductive layer, and connected to the second pad layer, and
a source connection conductive layer having an upper surface in contact with a lower surface of the first conductive layer, the source connection conductive layer in contact with the source contact plug and the second pad layer.

10. The semiconductor device of claim 9 , wherein the source contact plug is spaced apart from the first conductive layer in the second opening, and is electrically connected to the first conductive layer through the second pad layer and the source connection conductive layer.

11. The semiconductor device of claim 9 , wherein a lower surface of the source contact plug is on a lower level than the lower surface of the first conductive layer.

12. The semiconductor device of claim 9 , wherein the source connection conductive layer surrounds a lower portion of the source contact plug below the first conductive layer.

13. The semiconductor device of claim 9 , wherein
the source connection conductive layer has a hole penetrating through at least a portion of the source connection conductive layer below the second opening of the first conductive layer, and
the source contact plug extends into the hole of the source connection conductive layer.

14. The semiconductor device of claim 13 , wherein
the source contact plug includes a firs

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seungyoon
• Jun Junghoon
• Chun Sanghun
• Han Jeehoon

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/792

  between multiple chips · CPC title