Semiconductor device including vertical channel layer

Patent metadata

Field	Value
Publication number	US-10411033-B2
Application number	US-201815993756-A
Country	US
Kind code	B2
Filing date	May 31, 2018
Priority date	Jun 21, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of channel structures on a substrate, each channel structure of the plurality of channel structures extending in a first direction perpendicular to an upper surface of the substrate, and having a gate insulating layer and a channel layer;
a common source extension region between the substrate and the plurality of channel structures, the common source extension region including a first semiconductor layer having an n-type conductivity;
a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the plurality of channel structures in the first direction; and
a common source region on the substrate, the common source region being in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity,
wherein the gate insulating layer of each of the plurality of channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

2. The semiconductor device as claimed in claim 1 , wherein a portion of the gate insulating layer extends from a sidewall of the channel layer, and the portion of the gate insulating layer covers the upper surface, a sidewall, and a portion of the bottom surface of the common source extension region.

3. The semiconductor device as claimed in claim 1 , wherein a portion of the bottom surface of the common source extension region is in contact with the common source region.

4. The semiconductor device as claimed in claim 1 , wherein an upper surface of the second semiconductor layer is at a level that is lower than or identical to the upper surface of the common source extension region.

5. The semiconductor device as claimed in claim 1 , further comprising:
a base layer between the common source extension region and the substrate and having an n-type conductivity; and
a lower insulating layer between the base layer and the common source extension region.

6. The semiconductor device as claimed in claim 5 , wherein a bottom surface of the common source region is at an identical level as a bottom surface of the base layer, and
the plurality of channel structures are electrically insulated from the substrate by the lower insulating layer.

7. The semiconductor device as claimed in claim 5 , wherein a portion of the gate insulating layer is between the common source extension region and the lower insulating layer.

8. The semiconductor device as claimed in claim 5 , wherein an undercut region is in a portion of the lower insulating layer between the common source extension region and the base layer, and the common source region includes a protrusion that fills the undercut region and contacts the lower insulating layer.

9. The semiconductor device as claimed in claim 1 , wherein the common source region further includes a support layer that is on the second semiconductor layer, spaced apart from the common source extension region, and electrically connected to the common source extension region via the second semiconductor layer of the common source region.

10. The semiconductor device as claimed in claim 9 , wherein an upper surface of the support layer is at a higher level than the upper surface of the common source extension region.

11. The semiconductor device as claimed in claim 9 , further comprising a common source line on the common source region, wherein the support layer surrounds a lower sidewall of the common source line.

12. A semiconductor device, comprising:
a base layer on a substrate and having an n-type conductivity;
a common source extension region on the base layer and including a first semiconductor layer having an n-type conductivity;
a plurality of channel structures on the common source extension region and extending in a first direction perpendicular to an upper surface of the substrate, each of the plurality of channel structures having a gate insulating layer and a channel layer;
a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the plurality of channel structures in the first direction; and
a common source region on the substrate, the common source region being in contact with a portion of a bottom surface of the common source extension region and including a second semiconductor layer having an n-type conductivity,
wherein a portion of the gate insulating layer of each of the plurality of channel structures extends to cover an upper surface and at least a portion of the bottom surface of the common source extension region.

13. The semiconductor device as claimed in claim 12 , further comprising a lower insulating layer between the base layer and the common source extension region, the plurality of channel structures being electrically insulated from the substrate by the lower insulating layer.

14. The semiconductor device as claimed in claim 13 , wherein an undercut region is in a portion of the lower insulating layer between the common source extension region and the base layer, the common source region including a protrusion that fills the undercut region and contacts the lower insulating layer.

15. The semiconductor device as claimed in claim 12 , wherein a bottom surface of the common source region is at an identical level as a bottom surface of the base layer.

16. The semiconductor device as claimed in claim 12 , wherein the common source region includes a support layer on the second semiconductor layer and having an upper surface that is at a higher level than the upper surface of the common source extension region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kwang-Soo
• Kim Yong-Seok
• Kim Tae-Hun
• Bae Min-Kyung
• Jang Jae-Hoon
• Kanamori Kohji

Classifications

• H01L29/0847

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title