Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-12354636-B2
Application number	US-202118025457-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 22, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A semiconductor device with low power consumption that is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, an input terminal of the second FTJ element, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a second terminal of the third transistor. For data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with data. For data reading, a voltage that does not cause a change in polarization is applied between the input terminal of the first FTJ element and the output terminal of the second FTJ element, a potential is supplied to the gate of the second transistor, and a current or voltage corresponding to data is obtained from the first terminal of the second transistor.

First claim

The invention claimed is:

1. A semiconductor device comprising a first transistor, a second transistor, a first FTJ element and a second FTJ element,
wherein each of the first FTJ element and the second FTJ element is a ferroelectric tunnel junction element,
wherein each of the first FTJ element and the second FTJ element comprises an input terminal, a tunnel insulating film, a dielectric, and an output terminal,
wherein in each of the first FTJ element and the second FTJ element, the input terminal, the tunnel insulating film, the dielectric, and the output terminal are stacked in this order, and
wherein one of a source and a drain of the first transistor is electrically connected to the output terminal of the first FTJ element, the input terminal of the second FTJ element, and a gate of the second transistor.

2. The semiconductor device according to claim 1 ,
wherein the tunnel insulating film comprises silicon oxide or silicon nitride, and
wherein the dielectric comprises an oxide comprising one or both of hafnium and zirconium.

3. The semiconductor device according to claim 1 , wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor.

4. The semiconductor device according to claim 1 , further comprising a third transistor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor.

5. The semiconductor device according to claim 4 , wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor.

6. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a housing.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Kimura Hajime
• Kunitake Hitoshi

Classifications

• G11C11/2293

  Timing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C13/00

  Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title