Low power and area efficient memory receiver

Patent metadata

Field	Value
Publication number	US-10014036-B1
Application number	US-201615393951-A
Country	US
Kind code	B1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

First claim

We claim:

1. An electronic processing system, comprising:
a memory component; and
an electronic component communicatively coupled to the memory component, the electronic component including a receiver to receive a signal from the memory component,
wherein the receiver comprises:
high pass components to pass high frequency components of the signal;
low pass components to pass low frequency components of the signal; and
an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components,

wherein the low pass components include a level shifter to shift a common mode voltage level of the signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices for the memory component.

2. The electronic processing system of claim 1 , wherein the amplifier comprises a self-biased inverter.

3. The electronic processing system of claim 2 , wherein the high pass components, the low pass components, and the amplifier are all part of a single stage, continuous time linear equalizer which is electronically adjustable to receive signals from the at least two different types of memory devices.

4. The electronic processing system of claim 2 , wherein the high pass components comprise a capacitor which has at least two orders of magnitude greater impedance than a connected termination circuit below the bandwidth of the receiver.

5. The electronic processing system of claim 2 , wherein the level shifter comprises a variable resistor network which has at least two orders of magnitude greater resistance than a connected termination circuit.

6. The electronic processing system of claim 5 , wherein the variable resistor network comprises:
a first variable resistor having a first node coupled to a common input front end voltage and a second node coupled to the input of the self-biased inverter; and
a second variable resistor having a first node coupled to the input of the self-biased inverter and a second node coupled to ground,
wherein a value for each of the first and second variable resistors is electronically adjustable to provide the switch threshold voltage at the input of the self-biased inverter for the at least two different types of memory devices.

7. The electronic processing system of claim 6 , wherein the first and second variable resistors are each transistor-based.

8. The electronic processing system of claim 7 , wherein the at least two different types of memory devices include a first type of memory device, a second type of memory device, and a third type of memory device,
and wherein for the first type of memory device the first variable resistor is adjusted to be substantially off and the second variable resistor is adjusted to be substantially off,
and wherein for the second type of memory device the first variable resistor is adjusted to be substantially off and the second variable resistor is adjusted to be substantially on,
and wherein for the third type of memory device the first variable resistor is adjusted to be substantially on and the second variable resistor is adjusted to be substantially off.

9. The electronic processing system of claim 1 , wherein a memory device included in the memory component comprises one of a double data rate dynamic random access memory and a low power double data rate dynamic random access memory.

10. The electronic processing system of claim 1 , wherein the electronic component comprises one of a central processor unit and a memory controller.

11. The electronic processing system of claim 1 , wherein the electronic component is further to determine a type of a memory device included in the memory component which is communicatively coupled to the electronic component and to configure the level shifter in accordance with the type of the memory device.

12. A receiver apparatus, comprising:
high pass components to pass high frequency components of an input signal;
low pass components to pass low frequency components of the input signal; and
an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components,
wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices.

13. The receiver apparatus of claim 12 , wherein the amplifier comprises a self-biased inverter.

14. The receiver apparatus of claim 13 , wherein the high pass components, the low pass components, and the amplifier are all part of a single stage, continuous time linear equalizer which is electronically adjustable to receive signals from the at least two different types of memory devices.

15. The receiver apparatus of claim 13 , wherein the high pass components comprise a capacitor which has at least two orders of magnitude greater impedance than a connected termination circuit.

16. The receiver apparatus of claim 13 , wherein the level shifter comprises a variable resistor network which has at least two orders of magnitude greater resistance than a connected termination circuit.

17. The receiver apparatus of claim 16 , wherein the variable resistor network comprises:
a first variable resistor having a first node coupled to a common input front end voltage and a second node coupled to the input of the self-biased inverter; and
a second variable resistor having a first node coupled to the input of the self-biased inverter and a second node coupled to ground,
wherein a value for each of the first and second variable resistors is electronically adjustable to provide the switch threshold voltage at the input of the self-biased inverter for the at least two different types of memory devices.

18. The receiver apparatus of claim 17 , wherein the first and second variable resistors are each transistor-based.

19. The receiver apparatus of claim 18 , wherein the at least two different types of memory devices include a first type of memory device, a second type of memory device, and a third type of memory device,
and wherein for the first type of memory device the first variable resistor is adjusted to be substantially off and the second variable resistor is adjusted to be substantially off,
and wherein for the second type of memory device the first variable resistor is adjusted to be substantially off and the second variable resistor is adjusted to be substantially on,
and wherein for the third type of memory device the first variable resistor is adjusted to be substantially on and the second variable resistor is adjusted to be substantially off.

Assignees

• Intel Corp

Inventors

• Zhou Kuan
• Querbach Bruce
• Pan Li

Classifications

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title