Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin

Patent metadata

Field	Value
Publication number	US-9728259-B1
Application number	US-201615070621-A
Country	US
Kind code	B1
Filing date	Mar 15, 2016
Priority date	Mar 15, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability. One non-limiting example of an NV-CAM cell that employs MTJ differential sensing is a ten (10) transistor (10T)-four (4) MTJ (10T-4MTJ) NV-TCAM cell.

First claim

What is claimed is:

1. A non-volatile (NV)-content addressable memory (CAM) cell, comprising:
a differential magnetic tunnel junction (MTJ) cell circuit, comprising:
a first MTJ circuit configured to receive search data on a search line and complementary search data, complementary to the search data, on a complementary search line;
a second MTJ circuit configured to receive the search data on the search line and the complementary search data on the complementary search line; and
the differential MTJ cell circuit configured to generate a differential cell voltage comprising a data cell voltage on a data node and a reference cell voltage on a reference node, in response to:
a first differential resistance level between the first MTJ circuit and the second MTJ circuit indicating a match condition of the search data, in response to the search data being in an activation state on the search line; and
a second differential resistance level between the first MTJ circuit and the second MTJ circuit indicating the match condition of the search data, in response to the complementary search data being in the activation state on the complementary search line; and

a cross-coupled metal oxide semiconductor (MOS) amplifier circuit, comprising:
a first transistor configured to be activated in response to the data cell voltage on the data node indicating a mismatch condition with the search data, to couple a supply voltage rail to the reference node; and a second transistor configured to be activated in response to the reference cell voltage on the reference node indicating the match condition with the search data, to couple the supply voltage rail to the data node.

2. The NV-CAM cell of claim 1 , further comprising a decoupling transistor configured to be activated in response to one of the data cell voltage and the reference cell voltage to control a voltage level of a match line indicating the match condition or the mismatch condition.

3. The NV-CAM cell of claim 1 , wherein:
the first transistor is further configured to be deactivated in response to the data cell voltage on the data node indicating the match condition with the search data, to decouple the supply voltage rail from the reference node; and
the second transistor is further configured to be deactivated in response to the reference cell voltage on the reference node indicating the mismatch condition with the search data, to decouple the supply voltage rail from the data node.

4. The NV-CAM cell of claim 1 , wherein:
the first MTJ circuit comprises:
a first MTJ device configured to be coupled between the reference node and a first bit line in response to the search data being in the activation state on the search line; and
a second MTJ device configured to be coupled between the reference node and the first bit line in response to the complementary search data being in the activation state on the complementary search line; and

the second MTJ circuit comprises:
a third MTJ device configured to be coupled between the data node and a second bit line in response to the complementary search data being in the activation state on the complementary search line; and
a fourth MTJ device configured to be coupled between the data node and the second bit line in response to the search data being in the activation state on the search line.

5. The NV-CAM cell of claim 4 , wherein:
the first MTJ device is further configured to be decoupled between the reference node and the first bit line in response to the search data being in a deactivation state on the search line;
the second MTJ device is further configured to be decoupled between the reference node and the first bit line in response to the complementary search data being in the deactivation state on the complementary search line;
the third MTJ device is further configured to be decoupled between the data node and the second bit line in response to the complementary search data being in the deactivation state on the complementary search line; and
the fourth MTJ device is further configured to be decoupled between the data node and the second bit line in response to the search data being in the deactivation state on the search line.

6. The NV-CAM cell of claim 4 , wherein:
in response to the search data being in the activation state on the search line, the first MTJ device is further configured to generate a first resistance and the fourth MTJ device is further configured to generate a fourth resistance different from the first resistance to provide the first differential resistance level between the first MTJ circuit and the second MTJ circuit indicating the match condition of the search data; and
in response to the complementary search data being in the activation state on the complementary search line, the second MTJ device is further configured to generate a second resistance and the third MTJ device is further configured to generate a third resistance different from the second resistance to provide the second differential resistance level between the first MTJ circuit and the second MTJ circuit indicating the match condition of the search data.

7. The NV-CAM cell of claim 4 , wherein:
the first MTJ circuit further comprises:
a first access circuit configured to selectively control coupling of the first MTJ device between the reference node and the first bit line in response to the search data being in the activation state on the search line; and
a second access circuit configured to selectively control coupling of the second MTJ device between the reference node and the first bit line in response to the complementary search data being in the activation state on the complementary search line; and

the second MTJ circuit further comprises:
a third access circuit configured to selectively control coupling of the third MTJ device between the data node and the second bit line in response to the complementary search data in the activation state on the complementary search line; and
a fourth access circuit configured to selectively control coupling of the fourth MTJ device between the data node and the second bit line in response to the search data being in the activation state on the search line.

8. The NV-CAM cell of claim 4 , wherein:
the first MTJ circuit is configured to:
store write data from the first bit line into the first MTJ device, in response to the write data being asserted on the first bit line and complementary write data being asserted on the second bit line; and
store write data from the second bit line into the second MTJ device, in response to write data being asserted on the second bit line and complementary write data being asserted on the first bit line; and

the second MTJ circuit is configured to:
store the write data from the second bit line into the third MTJ device, in response to the write data being asserted on the second bit line and the complementary write data being asserted on the first bit line; and
store the write data from the first bit line into the fourth MTJ device, in response to the write data being asserted on the first bit line and the complementary write data being asserted on the second bit line.

9. The NV-CAM cell of claim 1 , further comprising a pre-charge circuit configured to couple the reference node to the supply voltage rail to pre-charge the reference node and the data node to a supply voltage on the supply voltage rail, in response to a pre-charge signal indicating a pre-charge mode.

10. The NV-CAM cell of claim 9 , wherein the differential MTJ cell circuit is further configured to be decoupled from the data node and the reference node in response to the search data being in a deactivation state on the search line and the complement

Assignees

• Qualcomm Technologies Inc
• Industry-Academic Cooperation Foundation Yonsei Univ

Inventors

• Jung Seong-Ook
• Song Byung Kyu
• Na Taehui
• Kim Jung Pill
• Kang Seung Hyuk

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C15/046 Primary

  using non-volatile storage elements · CPC title

• G11C15/02

  using magnetic elements · CPC title