Multiple instruction issuance with parallel inter-group and intra-group picking

Patent metadata

Field	Value
Publication number	US-10089114-B2
Application number	US-201615086052-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.

First claim

What is claimed is:

1. A method of picking instruction in a scheduler, the method comprising:
picking, by an inter-group picker of the scheduler, ready groups such that
multiple ready groups are picked when there are two or more ready groups among a plurality of groups, each group including one or more instructions, each ready group being a group with at least one of the one or more instructions being a ready instruction, each ready instruction being an instruction that has all of its operands available such that the instruction is enabled to bid for execution by an execution unit of a processor core, and
a single ready group is picked when the single ready group is the only ready group among the plurality of groups; and

picking, by an intra-group picker of the scheduler, ready instructions such that
one ready instruction is picked from each of the multiple ready groups when the multiple ready groups are picked, and
multiple ready instructions are picked from the single ready group when the single ready group is picked,

wherein the scheduler is a scheduler of the processor core, and
wherein the inter-group picker and the intra-group picker are implemented in hardware.

2. The method of claim 1 , picking the ready groups and picking the ready instructions occurring in parallel.

3. The method of claim 1 , picking the ready instructions comprising picking the ready instructions in an order of priority.

4. The method of claim 3 , the order of priority being from an oldest ready instruction to a newest ready instruction.

5. The method of claim 1 ,
picking the multiple ready groups comprising picking an oldest ready group and a newest ready group when there are two or more ready groups among the plurality of groups,
picking the one ready instruction each from each of the multiple ready groups comprising picking one ready instruction from each of the oldest and newest ready groups, and
picking the multiple ready instructions from the single ready group comprising picking up to two ready instructions from the single ready group.

6. The method of claim 5 , further comprising setting a grant new line of an inter-group picker of the scheduler when a group associated with the grant new line is the newest ready group.

7. The method of claim 6 , further comprising replacing a first ready instruction of an existing newest group on the grant new line with a second ready instruction of a group that is newer than the existing newest group.

8. The method of claim 6 , further comprising setting a grant old line of the inter-group picker of the scheduler when a group associated with the grant old line is the oldest ready group.

9. The method of claim 8 , further comprising replacing a first ready instruction of an existing oldest group on the grant old line with a second ready instruction of a group that is older than the existing oldest group.

10. The method of claim 8 , further comprising the inter-group picker indicating to an intra-group picker to pick either one or two instructions based on the grant new line and the grant old line.

11. The method of claim 5 , picking the ready instructions comprising picking one or two ready instructions from a group associated with an intra-group picker based on any combination of the following:
a number of instructions bidding in the associated group,
a number of instructions already picked by lower intra-group picker(s), and
whether or not there are ready groups other than the associated group,
wherein each lower intra-group picker is associated with a group whose instructions have greater priorities than the instructions of the associated group.

12. The method of claim 11 , further comprising the intra-group picker notifying a higher intra-group picker a number of instructions picked by the intra-group picker and the lower intra-group picker(s),
wherein the higher intra-group picker is associated with a group whose instructions have lesser priorities than the instructions of the associated group.

13. A non-transitory computer-readable medium having a code recorded thereon that causes a computer to perform a method of picking instruction in a scheduler, the method comprising:
picking, by an inter-group picker of a scheduler, ready groups such that
multiple ready groups are picked when there are two or more ready groups among a plurality of groups, each group including one or more instructions, each ready group being a group with at least one of the one or more instructions being a ready instruction, each ready instruction being an instruction that has all of its operands available such that the instruction is enabled to bid for execution by an execution unit of a processor core, and
a single ready group is picked when the single ready group is the only ready group among the plurality of groups; and

picking, by an intra-group picker of the scheduler, ready instructions such that
one ready instruction is picked from each of the multiple ready groups when the multiple ready groups are picked, and
multiple ready instructions are picked from the single ready group when the single ready group is picked.

14. A scheduler, comprising:
an inter-group picker configured to pick:
multiple ready groups when there are two or more ready groups among a plurality of groups, each group including one or more instructions, each ready group being a group with at least one of the one or more instructions being a ready instruction, each ready instruction being an instruction that has all of its operands available such that the instruction is enabled to bid for execution by an execution unit of a processor core, and
a single ready group when the single ready group is the only ready group among the plurality of groups; and

an intra-group picker configured to pick:
one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and
multiple ready instructions from the single ready group when the inter-group picker picks the single ready group,

wherein the scheduler is a scheduler of the processor core, and
wherein the inter-group picker and the intra-group picker are implemented in hardware.

15. The scheduler of claim 1 , the inter-group picker being configured to pick the ready groups and the intra-group picker being configured to pick the ready instructions in parallel.

16. The scheduler of claim 1 , the intra-group picker being configured to pick the ready instructions in an order of priority.

17. The scheduler of claim 16 , the order of priority being from an oldest ready instruction to a newest ready instruction.

18. The scheduler of claim 1 ,
the inter-group picker being configured to pick an oldest ready group and a newest ready group when there are two or more ready groups among the plurality of groups, and
the intra-group picker being configured to pick:
one ready instruction from each of the oldest and newest ready groups when the inter-group picker picks the oldest and newest ready groups, and
up to two ready instructions the single ready group when the inter-group picker picks the single ready group.

19. The scheduler of claim 18 , the inter-group picker comprising a grant new line which when evaluated as being set indicates that a group associated with the grant new line is the newest ready group.

20. The scheduler of claim 19 , the inter-group picker being configured to replace a first ready instruction of an existing newest group on the grant new line by a second ready instruction of a group that is

Assignees

• Qualcomm Inc

Inventors

• Kulkarni Milind Ram
• Al Sheikh Rami Mohammad A
• Damodaran Raguram

Classifications

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title