Non-recirculating label switching packet processing

Patent metadata

Field	Value
Publication number	US-10027587-B1
Application number	US-201615085823-A
Country	US
Kind code	B1
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Disclosed herein is an apparatus for processing an Internet Protocol (IP) header and label switching (LS) headers of a packet in a pipeline. The apparatus includes an LS header processing circuit configured to select a first operation for the packet using an LS header from the packet, and an IP header processing circuit configured to perform an IP lookup to select a second operation for the packet. The apparatus further includes a tunnel initiation circuit configured to initiate an LS tunnel or IP tunnel. The LS header processing circuit, the IP header processing circuit, and the tunnel initiation circuit are operable to operate sequentially on a same packet and concurrently on different packets in a pipeline. Each of these circuits is operable to be bypassed based on an outermost header in the packet, or the selected one of the first operation or the second operation.

First claim

What is claimed is:

1. An integrated circuit for routing, in a pipeline, a plurality of packets each having a multiprotocol label switching (MPLS) header or an internet protocol (IP) header, the integrated circuit comprising:
a tunnel initiation circuit configured to initiate an MPLS tunnel or IP tunnel;
an MPLS header processing circuit configured to select, using an MPLS lookup table and the MPLS header from a packet of the plurality of packets, a first operation of modifying the MPLS header, the MPLS header including an MPLS label;
an IP header processing circuit configured to perform an IP lookup on the IP header of the packet, using an IP lookup table, to select a second operation of forwarding the packet to an IP router or the tunnel initiation circuit; and
an MPLS outer label determination circuit configured to determine a first MPLS label for the packet;
wherein the tunnel initiation circuit, the MPLS header processing circuit, the MPLS outer label determination circuit, and the IP header processing circuit are operable to operate sequentially on a same packet and concurrently on different packets; and
wherein each of the multiple tunnel initiation circuit, the MPLS header processing circuit, the MPLS outer label determination circuit, and the IP header processing circuit is operable to be bypassed based on an outermost header in the packet, or the selected one of the first operation or the second operation.

2. The integrated circuit of claim 1 ,
wherein the MPLS header processing circuit is operable to determine an operation of removing the MPLS header and terminating a current MPLS tunnel;
wherein the IP header processing circuit is operable to determine an operation of forwarding the packet to the tunnel initiation circuit to start a new MPLS tunnel for the packet; and
wherein the tunnel initiation circuit is operable to determine a second MPLS label for the packet, the first label to be added on top of the second label in an MPLS label stack for the packet.

3. The integrated circuit of claim 1 ,
wherein the MPLS header processing circuit is operable to be bypassed when the outermost header of the packet is the IP header;
wherein the IP header processing circuit is operable to determine an operation of forwarding the packet to the tunnel initiation circuit; and
wherein the tunnel initiation circuit is operable to determine a second MPLS label for the packet, the first label to be added on top of the second label in an MPLS label stack for the packet.

4. The integrated circuit of claim 1 ,
wherein the MPLS header processing circuit is operable to determine an operation of removing the MPLS header; and
wherein the IP header processing circuit is operable to determine an operation of forwarding the packet to the IP router.

5. The integrated circuit of claim 1 ,
wherein the MPLS lookup table includes a plurality of entries, each entry including a virtual routing and forwarding identifier (VRFID); and
wherein the IP lookup table corresponds to the VRFID associated with the packet.

6. An apparatus comprising:
a label switching (LS) header processing circuit configured to select, using an LS lookup table and an LS header from a packet, a first operation for the packet, the LS header including an LS label;
an Internet Protocol (IP) header processing circuit configured to perform an IP lookup on an IP header of the packet, using an IP lookup table, to select a second operation for the packet; and
a tunnel initiation circuit configured to initiate an LS tunnel or IP tunnel;
wherein the LS header processing circuit, the IP header processing circuit, and the tunnel initiation circuit are operable to operate sequentially on a same packet and concurrently on different packets in a pipeline; and
wherein each of the LS header processing circuit, the IP header processing circuit, and the tunnel initiation circuit is operable to be bypassed based on an outermost header in the packet, or the selected one of the first operation or the second operation.

7. The apparatus of claim 6 ,
wherein the LS lookup table includes a plurality of entries, each entry including a virtual routing and forwarding identifier (VRFID); and
wherein the IP lookup table is selected using the VRFID associated with the packet.

8. The apparatus of claim 6 , wherein the LS header in the packet is a multiprotocol label switching (MPLS) header.

9. The apparatus of claim 6 , further comprising:
an LS outer label determination circuit configured to determine a first LS label for the packet,
wherein the LS outer label determination circuit is operable to be bypassed based on the selected first operation or second operation.

10. The apparatus of claim 9 ,
wherein the first operation includes removing the LS header and terminating a current LS tunnel;
wherein the second operation includes forwarding the packet to the tunnel initiation circuit to start a new LS tunnel; and
wherein the tunnel initiation circuit is operable to determine a second LS label for the packet, the first label to be added on top of the second label in an LS label stack for the packet.

11. The apparatus of claim 9 ,
wherein the LS header processing circuit is operable to be bypassed when the outermost header of the packet is the IP header;
wherein the second operation includes forwarding the packet to the tunnel initiation circuit; and
wherein the tunnel initiation circuit is operable to determine a second LS label for the packet, the first LS label to be added on top of the second LS label in an LS label stack for the packet.

12. The apparatus of claim 9 ,
wherein the first operation includes replacing the LS label with the first LS label; and
wherein the IP header processing circuit and the tunnel initiation circuit are operable to be passed when the first operation includes replacing the LS label.

13. The apparatus of claim 6 ,
wherein the LS header processing circuit is operable to be bypassed when the outermost header of the packet is the IP header; and
wherein the tunnel initiation circuit is operable to be bypassed when the second operation includes forwarding the packet to an IP router.

14. The apparatus of claim 6 ,
wherein the first operation includes removing the LS label;
wherein the second operation includes forwarding the packet to an IP router; and
wherein the tunnel initiation circuit is operable to be bypassed when the second operation includes forwarding the packet to the IP router.

15. The apparatus of claim 6 ,
wherein the packet includes a plurality of LS headers, each LS header including an LS label, the LS labels forming an LS label stack;
wherein the LS header processing circuit includes two circuits in a pipeline;
wherein a first circuit of the LS header processing circuit is operable to process a first LS label in the LS label stack;
wherein a second circuit of the LS header processing circuit is operable to process a second LS label in the LS label stack; and
wherein the two circuits of the LS header processing circuit are operable to process LS labels of a same packet sequentially and process LS labels of different packets concurrently.

16. The apparatus of claim 6 , wherein the apparatus is one of an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system-on-chip (SoC), a system-in-package (SiP), and a portion of an ASIC, FPGA, SoC, or SiP.

17. A computer-implemented method for processing packets by a pipeline circuit, the method comprising:
receiving a packet including a label switching (LS) header and an Inter

Assignees

• Amazon Tech Inc

Inventors

• O'Brien Kari Ann
• Volpe Thomas A
• Singh Bijendra

Classifications

• H04L45/50 Primary

  using label swapping, e.g. multi-protocol label switch [MPLS] · CPC title

• H04L45/7452

  Multiple parallel or consecutive lookup operations (lookup operation involving Bloom filters H04L45/7459) · CPC title

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L69/325

  in the network layer [OSI layer 3], e.g. X.25 (H04L69/16 takes precedence) · CPC title