Method for manufacturing an OxRAM type resistive memory cell

Patent metadata

Field	Value
Publication number	US-12349605-B2
Application number	US-202017618295-A
Country	US
Kind code	B2
Filing date	Jun 11, 2020
Priority date	Jun 12, 2019
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 107Ω and 3·109Ω; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

First claim

The invention claimed is:

1. A method for manufacturing an OxRAM type resistive memory cell comprising a silicon oxide layer, said method comprising:
determining values of manufacturing parameters such that the resistive memory cell has an initial resistance comprised between 10 7 Ω and 3·10 9 Ω, the initial resistance being an electrical resistance obtained before a conductive filament is formed for the first time and measured by applying a measuring voltage of 100 mV;
forming on a substrate a stack successively comprising a first electrode, the silicon oxide layer and a second electrode, by applying said manufacturing parameter values,
wherein at least one of the manufacturing parameters is chosen among a thickness of the second electrode, a thickness of the silicon oxide layer, a proportion of oxygen in the silicon oxide layer and a porous or non-porous state of the silicon oxide layer.

2. The method according to claim 1 , wherein the manufacturing parameters are a thickness of the second electrode, a thickness of the silicon oxide layer and a proportion of oxygen in the silicon oxide layer.

3. The method according to claim 2 , wherein the silicon oxide is porous and wherein the proportion of oxygen in the silicon oxide layer is comprised between 1.6 and 2.

4. The method according to claim 3 , wherein the proportion of oxygen in the silicon oxide layer is comprised between 1.8 and 1.9.

5. The method according to claim 2 , wherein the silicon oxide is porous and wherein the thickness of the silicon oxide layer is comprised between 4 nm and 7 nm.

6. The method according to claim 2 , wherein the silicon oxide is porous and wherein the thickness of the second electrode is comprised between 3 nm and 7 nm.

7. The method according to claim 2 , wherein the silicon oxide is non-porous and wherein the proportion of oxygen in the silicon oxide layer is comprised between 1 and 1.6.

8. The method according to claim 7 , wherein the silicon oxide is non-porous and wherein the proportion of oxygen in the silicon oxide layer is comprised between 1.2 and 1.4.

9. The method according to claim 2 , wherein the silicon oxide is non-porous and wherein the thickness of the silicon oxide layer is comprised between 3 nm and 4 nm.

10. The method according to claim 2 , wherein the silicon oxide is non-porous and wherein the thickness of the second electrode is comprised between 4 nm and 6 nm.

11. The method according to claim 1 , wherein the silicon oxide layer is formed by cathodic sputtering.

12. The method according to claim 1 , wherein the first and second electrodes are formed by cathodic sputtering.

13. The method according to claim 1 , wherein the first electrode is made of titanium nitride and the second electrode is made of titanium.

14. The method according to claim 1 , wherein the resistive memory cell has an initial resistance comprised between 3·10 7 Ω and 10 9 Ω.

15. A method for manufacturing an OxRAM type resistive memory cell comprising a silicon oxide layer, said method comprising:
determining values of manufacturing parameters such that the resistive memory cell has an initial resistance comprised between 10 7 Ω and 3·10 9 Ω;
forming on a substrate a stack successively comprising a first electrode, the silicon oxide layer and a second electrode, by applying said manufacturing parameter values,
wherein the manufacturing parameters are a thickness of the second electrode, a thickness of the silicon oxide layer and a proportion of oxygen in the silicon oxide layer, and
wherein
the silicon oxide is porous and the proportion of oxygen in the silicon oxide layer is comprised between 1.6 and 2, or
the silicon oxide is porous and the thickness of the second electrode is comprised between 3 nm and 7 nm.

16. A method for manufacturing an OxRAM type resistive memory cell comprising a silicon oxide layer, said method comprising:
determining values of manufacturing parameters such that the resistive memory cell has an initial resistance comprised between 10 7 Ω and 3·10 9 Ω;
forming on a substrate a stack successively comprising a first electrode, the silicon oxide layer and a second electrode, by applying said manufacturing parameter values,
wherein the manufacturing parameters are a thickness of the second electrode, a thickness of the silicon oxide layer and a proportion of oxygen in the silicon oxide layer, and
wherein the silicon oxide is non-porous and the thickness of the second electrode is comprised between 4 nm and 6 nm.

17. A method for manufacturing an OxRAM type resistive memory cell comprising a silicon oxide layer, said method comprising:
determining values of manufacturing parameters such that the resistive memory cell has an initial resistance comprised between 10 7 Ω and 3·10 9 Ω;
forming on a substrate a stack successively comprising a first electrode, the silicon oxide layer and a second electrode, by applying said manufacturing parameter values,
wherein the first electrode is made of titanium nitride and the second electrode is made of titanium.

Assignees

• Commissariat Energie Atomique
• Weebit Nano Ltd

Inventors

• Molas Gabriel
• Piccolboni Guiseppe
• Regev Amir
• Castellan Gaël
• Nodin Jean-François

Classifications

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• H10N70/883 Primary

  Oxides or nitrides · CPC title

• H10N70/841

  Electrodes · CPC title