Fabrication method of vertical type semiconductor memory apparatus
US-9196832-B2 · Nov 24, 2015 · US
Addressable siox memory array with incorporated diodes
US2016276411A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016276411-A1 |
| Application number | US-201615171196-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 2, 2016 |
| Priority date | Aug 26, 2011 |
| Publication date | Sep 22, 2016 |
| Grant date | — |
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Abstract
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Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiO x , SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.
First claim
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What is claimed is: 1 . A method of forming a resistive memory cell, wherein the method comprises: depositing doped silicon on a substrate, wherein the substrate is an insulating substrate; depositing a first electrode on the insulating substrate; depositing a diode; depositing a resistive memory material, wherein the resistive memory material is selected from the group consisting of SiO x , SiO x H, SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 or equal to or less than 2; and depositing a second electrode. 2 . The method of claim 1 , wherein the resistive memory material is deposited on the first electrode; and the diode is deposited on the resistive memory material. 3 . The method of claim 1 , wherein diode is deposited on the first electrode. 4 . The method of claim 3 , further comprising depositing a metallic layer on the diode, wherein the resistive memory material is deposited on the metallic layer. 5 . The method of claim 1 , wherein the first electrode is deposited on the doped silicon; and depositing a metallic layer on the doped silicon, wherein the resistive memory material is deposited on the metallic layer. 6 . The method of claim 1 , wherein the diode is selected from the group consisting of n-p diodes, p-n diodes, and Schottky diodes.
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- What does patent US2016276411A1 cover?
- Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiO x , SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or e…
- Who is the assignee on this patent?
- Tour James M, Yao Jun, Lin Jian, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H01L27/2463. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Sep 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).