Resistive memory

Patent metadata

Field	Value
Publication number	US-2016351256-A1
Application number	US-201414563375-A
Country	US
Kind code	A1
Filing date	Dec 8, 2014
Priority date	Dec 6, 2013
Publication date	Dec 1, 2016
Grant date	—

Abstract

A memory device includes one or more first semiconductor ridges formed on a first semiconductor wafer. The first semiconductor ridges are configured to be first electrodes. The memory device also includes one or more second semiconductor ridges formed on a second semiconductor wafer. The second semiconductor ridges are configured to be second electrodes and are placed orthogonally on top of the first semiconductor ridges forming a crossbar structure, with sharp edges of the first semiconductor ridges coupled to sharp edges of the second semiconductor ridges. Each area of coupling of a first semiconductor ridge and a second semiconductor ridge is configured to be a memory cell. In addition, the memory device includes a compound layer covering the sharp edges of at least one of the first semiconductor ridges or the second semiconductor ridges. The compound layer is configured to be a switching layer.

First claim

What is claimed is:

1 . A method for fabricating a resistive memory device, comprising:
immersing a semiconductor wafer into a first acidic solution; treating the semiconductor wafer in a second acidic solution for a predetermined time period; forming a compound layer on a surface of the semiconductor wafer based on treating the semiconductor wafer in the second acidic solution for the predetermined time period; and depositing a metal disk of predetermined thickness and diameter on the compound layer, wherein deposition of the metal disk includes applying a predetermined pressure at a known deposition rate that corresponds to a type of metal associated with the metal disk.

2 . The method of claim 1 , wherein the semiconductor wafer includes a doped silicon wafer, and wherein immersing the doped silicon wafer into the first acidic solution comprises:
immersing the doped silicon wafer into a 1:50 diluted hydrogen fluoric (HF) acid solution.

3 . The method of claim 1 , wherein the semiconductor wafer includes a doped silicon wafer, and wherein treating the doped silicon wafer in the second acidic solution for a predetermined time period comprises:
treating the doped silicon wafer in a 3:1 volume ratio solution of sulfuric acid to hydrogen peroxide (3:1 volume ratio of H 2 SO 4 :H 2 O 2 ) for a time period of 20 minutes.

4 . The method of claim 1 , wherein depositing the metal disk of predetermined thickness and diameter comprises:
depositing the metal disk with a thickness in a range of 12 to 24 nanometers and diameter in a range of 25 to 200 microns.

5 . The method of claim 1 , wherein the metal is selected from the group consisting of silicon (Si), platinum (Pt), copper (Cu), silver (Ag), palladium (Pd) or tungsten (W).

6 . The method of claim 5 , wherein applying a predetermined pressure at a known deposition rate comprises:
applying a base pressure in a range of 7×10 −7 torr; and applying a deposition rate in a range of 0.2 angstrom/second for platinum and 1.0 angstrom/second for copper.

7 . The method of claim 5 , wherein the compound layer is one of a silicon oxide (SiO x ) layer or a hydrogen silsesquioxane (HSQ) layer, and wherein forming the compound layer comprises:
forming the compound layer with a thickness in a range of 1 nanometer.

8 . The method of claim 7 , comprising:
connecting the semiconductor wafer to ground, wherein the semiconductor wafer is configured to act as a first electrode; connecting the metal disk to a voltage source, wherein the metal disk is configured to act as a second electrode; and configuring the silicon oxide layer as a switching layer by applying a first voltage that ranges from −2.6 volts for platinum to +0.6 volts for copper, wherein the silicon oxide layer is configured to be in a set state, and applying a second voltage that ranges from −0.9 volts for platinum to 1.3 volts for copper, wherein the silicon oxide layer is configured to be in a reset state.

9 . A memory device comprising:
one or more first semiconductor ridges coupled to a first semiconductor wafer using contact pads, wherein the first semiconductor ridges are configured to be wordlines; one or more second semiconductor ridges coupled to a second semiconductor wafer using contact pads and placed orthogonally on top of the first semiconductor ridges forming a crossbar structure, with sharp edges of the first semiconductor ridges coupled to sharp edges of the second semiconductor ridges, wherein the second semiconductor ridges are configured to be bitlines and wherein each area of coupling of a first semiconductor ridge and a second semiconductor ridge is configured to be a memory cell; a compound layer covering the sharp edges of at least one of the first semiconductor ridges or the second semiconductor ridges, wherein the compound layer is configured to be a switching layer; a ground connection coupled to the first semiconductor ridges; and a voltage source coupled to the second semiconductor ridges for application of a switching voltage to the compound layer, wherein each memory cell is operable to be in a set state by application of a first voltage and operable to be in a reset state by application of a second voltage using the voltage source and the ground connection.

10 . The memory device of claim 9 , wherein at least one of the first semiconductor ridges or the second semiconductor ridges include silicon ridges.

11 . The memory device of claim 9 , wherein at least one of the first semiconductor wafer or the second semiconductor wafer includes silicon dioxide (SiO 2 ) on silicon-on-insulator (SOI) wafer.

12 . The memory device of claim 9 , wherein the compound layer is one of a silicon oxide (Sift) layer or a hydrogen silsesquioxane (HSQ) layer.

13 . The memory device of claim 9 , wherein the semiconductor contact pads include silicon contact pads.

14 . The memory device of claim 9 , wherein the second semiconductor ridges are formed of metal that is selected from the group consisting of platinum (Pt), copper (Cu), silver (Ag), palladium (Pd) or tungsten (W).

15 . The memory device of claim 9 , wherein the compound layer has a thickness in an order of 1 nanometer.

16 . The memory device of claim 15 , wherein the first voltage is in a range of −2.6 volt to +0.6 volt, and the second voltage is in a range of −1.3 volt to −0.9 volt.

17 . The memory device of claim 9 , wherein an area of a memory cell is in a range of 4 F 2 , wherein F is a minimum feature size.

18 . A memory device comprising:
one or more first ridges formed on a first semiconductor wafer, wherein the first ridges are formed using a semiconductor material and are configured to be first electrodes; one or more second ridges that are placed orthogonally on top of the first semiconductor ridges forming a crossbar structure, with sharp edges of the first ridges coupled to sharp edges of the second ridges, wherein the second ridges are configured to be second electrodes and each area of coupling of a first ridge and a second ridge is configured to be a memory cell; and a compound layer covering the sharp edges of at least one of the first ridges or the second ridges, wherein the compound layer is configured to be a switching layer, wherein a resistance of the switching layer corresponding to a first memory cell is configured to be in a first state by applying a first set of voltages to a first ridge and a second ridge associated with the first memory cell and the resistance of the switching layer is configured to be in a second state by applying a second set of voltages to the first ridge and the second ridge associated with the first memory cell, wherein the first memory cell is configured to store a first value when the resistance of the switching layer is in the first state and the first memory cell is configured to store a second value when the resistance of the switching layer is in the second state.

19 . The memory device of claim 18 , further comprising a memory controller that is configured to:
measure the resistance of the switching layer that is associated with the first memory cell; and based on measuring the resistance of the switching layer, determine whether the first value or the second value is stored in the first memory cell.

20 . The memory device of claim 18 , wherein the second ridges are formed using one of a semiconductor material or a metal, wherein the semiconductor material is silicon (Si), and wherein the metal is one of platinum (Pt), copper (Cu), s

Assignees

• Univ Massachusetts

Inventors

• Xia Qiangfei

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• G11C2213/33

  Material including silicon · CPC title

• H01L45/1608

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic