Low temperature deposition for silicon-based conductive film

Patent metadata

Field	Value
Publication number	US-9269898-B2
Application number	US-201414341723-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Feb 7, 2014
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.

First claim

What is claimed is:

1. A memory cell, comprising:
a first electrode comprising a seed layer configured to facilitate activation of a doped semiconductor material;
a switching layer positioned adjacent the first electrode, and configured to switch from a first state to a second state in response to a first signal applied to the memory cell and further configured to switch from the second state to the first state in response to a second signal applied to the memory cell; and
a second electrode adjacent the switching layer;
wherein the first electrode further comprises a conductive p-type doped silicon compound that is activated, via the seed layer, at a temperature less than or equal to about 450 degrees Celsius during formation of the first electrode.

2. The memory cell of claim 1 , further comprising one or more barrier layers disposed between the switching layer and the first electrode or the second electrode, wherein the one or more barrier layers are configured to mitigate oxidation of the switching layer.

3. The memory cell of claim 2 , wherein the one or more barrier layers are selected from a group consisting of: Ti, TiN, and W.

4. The memory cell of claim 1 , wherein
the conductive p-type doped silicon compound is formed at least in part utilizing the seed layer.

5. The memory cell of claim 4 , wherein the seed layer is configured to facilitate concurrent depositing and activation of a p-type dopant.

6. The memory cell of claim 5 , wherein the seed layer comprises a SiGe compound.

7. The memory cell of claim 5 , wherein the conductive p-type doped silicon compound is subjected to a temperature less than about 450 degrees Celsius.

8. The memory cell of claim 5 , wherein the p-type doped silicon compound comprises a SiGe compound.

9. The memory cell of claim 1 , further comprising a substrate having a complementary metal oxide semiconductor (CMOS) circuit formed at least in part thereon.

10. The memory cell of claim 8 , wherein the seed layer is configured to facilitate crystallization of the p-type doped silicon compound.

11. The memory cell of claim 1 , wherein a barrier layer of the one or more barrier layers has a thickness in a range from about 20 Å to about 30 Å.

12. The memory cell of claim 1 , wherein the seed layer comprises a silane layer.

13. The memory cell of claim 12 , wherein the silane layer is configured to facilitate ion nucleation in a conductive p-type doped silicon compound at a temperature less than about 450 degrees Celsius.

14. The memory cell of claim 8 , wherein the SiGe compound comprises a boron trichloride deposition material that is activated within the SiGe compound concurrent to deposition.

15. The memory cell of claim 8 , wherein the seed layer comprises a silane layer, and wherein the SiGe compound is subjected to a temperature of about 430 degrees Celsius.

16. The memory cell of claim 8 , wherein the seed layer comprises a silane layer, and wherein the SiGe compound is subjected to a temperature of about 410 degrees Celsius.

17. The memory cell of claim 5 , wherein the p-type dopant comprises a boron trichloride deposition material.

18. The memory cell of claim 9 , wherein the conductive p-type doped silicon compound forms a portion of an interconnect between the CMOS circuit and the memory cell.

19. The memory cell of claim 9 , wherein the conductive p-type doped silicon compound forms a portion of a via layer that connects the CMOS circuit to a metal wire.

20. The memory cell of claim 9 , wherein the conductive p-type doped silicon compound forms an electrical connection between the CMOS circuit and a conductive wire of a memory device comprising the memory cell.

Assignees

• Crossbar Inc

Inventors

• Maxwell Steven Patrick
• Kim Kuk-Hwan
• Jo Sung Hyun

Classifications

• H01L45/16

  Electricity · mapped topic

• H01L27/249

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic