Interconnect architecture with silicon interposer and EMIB

Patent metadata

Field	Value
Publication number	US-12347783-B2
Application number	US-202418406018-A
Country	US
Kind code	B2
Filing date	Jan 5, 2024
Priority date	Dec 28, 2018
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

First claim

What is claimed is:

1. An electronic package, comprising:
a package substrate;
an interposer coupled to the package substrate with interconnects;
a first die stack on the interposer;
a second die stack on the interposer, the second die stack laterally spaced apart from the first die stack along a first direction;
a third die stack on the interposer, the third die stack laterally spaced apart from the second die stack along the first direction;
a fourth die stack on the interposer, the fourth die stack laterally spaced apart from the first die stack along a second direction, the second direction orthogonal to the first direction;
a fifth die stack on the interposer, the fifth die stack laterally spaced apart from the third die stack along the second direction, and the fifth die stack laterally spaced apart from the fourth die stack along the first direction; and
a die coupled to the package substrate, the die having a footprint greater than a footprint of the first die stack, greater than a footprint of the second die stack, greater than a footprint of the third die stack, greater than a footprint of the fourth die stack, and greater than a footprint of the fifth die stack.

2. The electronic package of claim 1 , further comprising:
a sixth die stack on the interposer, the fifth die stack laterally spaced apart from the second die stack along the second direction, and the sixth die stack laterally between the fourth die stack and the fifth die stack along the first direction.

3. The electronic package of claim 1 , wherein each of the first die stack, the second die stack, the third die stack, the fourth die stack, and the fifth die stack comprises an IC base die and a plurality of memory dies stacked over the IC base die.

4. The electronic package of claim 3 , wherein the plurality of memory dies have a footprint that is larger than a footprint of the IC base die.

5. The electronic package of claim 1 , wherein each of the first die stack, the second die stack, the third die stack, the fourth die stack, and the fifth die stack comprises a die cube.

6. The electronic package of claim 1 , wherein each of the first die stack, the second die stack, the third die stack, the fourth die stack, and the fifth die stack comprises field-programmable gate array (FPGA) dies.

7. The electronic package of claim 1 , further comprising:
the die on the package substrate; and
an interconnect bridge on the package substrate, wherein the interconnect bridge electrically couples the interposer to the die.

8. The electronic package of claim 1 , wherein the interposer comprises silicon.

9. The electronic package of claim 1 , wherein the interposer is a passive interposer.

10. The electronic package of claim 1 , wherein the interposer is an active interposer.

11. A system, comprising:
a board; and
an electronic package coupled to the board, the electronic package comprising:
a package substrate;
an interposer coupled to the package substrate with interconnects;
a first die stack on the interposer;
a second die stack on the interposer, the second die stack laterally spaced apart from the first die stack along a first direction;
a third die stack on the interposer, the third die stack laterally spaced apart from the second die stack along the first direction;
a fourth die stack on the interposer, the fourth die stack laterally spaced apart from the first die stack along a second direction, the second direction orthogonal to the first direction;
a fifth die stack on the interposer, the fifth die stack laterally spaced apart from the third die stack along the second direction, and the fifth die stack laterally spaced apart from the fourth die stack along the first direction; and
a die coupled to the package substrate, the die having a footprint greater than a footprint of the first die stack, greater than a footprint of the second die stack, greater than a footprint of the third die stack, greater than a footprint of the fourth die stack, and greater than a footprint of the fifth die stack.

12. The system of claim 11 , further comprising:
a communication chip coupled to the board.

13. The system of claim 11 , further comprising:
a camera coupled to the board.

14. The system of claim 11 , further comprising:
a battery coupled to the board.

15. The system of claim 11 , further comprising:
a display coupled to the board.

16. The system of claim 11 , further comprising:
a GPS coupled to the board.

17. The system of claim 11 , wherein the electronic package further comprises a sixth die stack on the interposer, the fifth die stack laterally spaced apart from the second die stack along the second direction, and the sixth die stack laterally between the fourth die stack and the fifth die stack along the first direction.

18. The system of claim 11 , wherein each of the first die stack, the second die stack, the third die stack, the fourth die stack, and the fifth die stack comprises an IC base die and a plurality of memory dies stacked over the IC base die.

19. The system of claim 18 , wherein the plurality of memory dies have a footprint that is larger than a footprint of the IC base die.

20. The system of claim 11 , wherein each of the first die stack, the second die stack, the third die stack, the fourth die stack, and the fifth die stack comprises a die cube.

Assignees

• Intel Corp

Inventors

• Hossain Md Altaf
• Nalamalpu Ankireddy
• Subbareddy Dheeraj
• Sankman Robert
• Mahajan Ravindranath V
• Mallik Debendra
• Viswanath Ram S
• Sane Sandeep B
• Srinivasan Sriram
• Agarwal Rajat
• Dasu Aravind
• Weber Scott
• Gutala Ravi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title