Top-side interconnection substrate for die-to-die interconnection

Patent metadata

Field	Value
Publication number	US-2016111406-A1
Application number	US-201414517397-A
Country	US
Kind code	A1
Filing date	Oct 17, 2014
Priority date	Oct 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

At least one method, apparatus and system disclosed involves a multi-die integrated circuit device. A first substrate portion having a first height is formed. A first device over the first substrate portion is formed. A second substrate portion having a second height is formed. A second device is formed over the second substrate portion. An interconnect substrate feature is formed above the first and second devices. The interconnect substrate is configured to accommodate a plurality of interconnect lines electrically coupling the first and second devices.

First claim

What is claimed is:

1 . A method for providing a multi-die integrated circuit device, comprising:
forming a first substrate portion having a first height; placing a first device over said first substrate portion; forming a second substrate portion having a second height; placing a second device over said second substrate portion; and forming an interconnect substrate feature above said first and second devices, wherein said interconnect substrate being configured to accommodate a plurality of interconnect lines for electrically coupling said first and second devices.

2 . The method of claim 1 , wherein forming said first substrate portion having said first height comprises:
forming a core substrate; and wherein said first height is greater than said second height.

3 . The method of claim 1 , wherein placing said first device over said first substrate portion comprises placing a processing device.

4 . The method of claim 1 , wherein placing said second substrate portion having said second height comprises placing a coreless substrate.

5 . The method of claim 1 , wherein forming said interconnect substrate feature above said first and second devices comprises forming a silicon feature adapted to accommodate high density interconnection features.

6 . The method of claim 1 , wherein placing said second device comprises placing a plurality of memory devices to form a memory stack.

7 . The method of claim 6 , further comprising determining a number of interconnection lines between said first and second devices, wherein said number of interconnection lines being proportional to the number of said memory devices in said memory stack.

8 . The method of claim 7 , further comprising forming said interconnection lines in said interconnect substrate feature.

9 . The method of claim 8 , wherein forming said interconnect substrate feature comprises forming a plurality of metal connection features between said interconnect substrate feature and said first and second devices for coupling said interconnection lines to said first and second devices.

10 . The method of claim 9 , wherein placing said plurality of memory devices comprises placing a plurality of metal connection features between each of said memory devices for interconnecting said memory devices.

11 . The method of claim 1 , wherein forming said first substrate portion having a first height comprises forming a core substrate having said first height that is based upon the height of said second device such that the top portion of said first device is in level with the top portion of said second device.

12 . An integrated circuit device, comprising:
a substrate comprising a first substrate portion having a first height and a second substrate portion having a second height; a first device positioned above said first substrate portion; a second device positioned above said second substrate portion; and an interconnect substrate feature positioned above said first and second devices, wherein said interconnect substrate feature comprises a plurality of interconnection lines for electrically coupling said first and second devices.

13 . The integrated circuit device of claim 12 , wherein said first substrate portion comprises a core and wherein said second substrate portion is a coreless substrate portion.

14 . The integrated circuit device of claim 12 , wherein said first height is greater than said second height, wherein the top portion of said first device is in level with the top portion of said second device.

15 . The integrated circuit device of claim 12 , wherein said interconnect substrate feature comprises a plurality of high density metal connection features for coupling electrical signal between said first and second devices.

16 . The integrated circuit device of claim 12 , wherein said first device is a processing device and said second device is a memory stack.

17 . The integrated circuit device of claim 16 , wherein said memory stack comprises a plurality of memory devices, wherein each of said memory devices comprises a plurality of high density metal connection features for coupling electrical signals between said memory devices.

18 . A system, comprising:
a semiconductor device processing system to provide an integrated circuit device, wherein said integrated circuit device comprises:
a substrate comprising a first substrate portion having a first height and a second substrate portion having a second height;
a first device positioned above said first substrate portion;
a second device positioned above said second substrate portion; and
an interconnect substrate feature positioned above said first and second devices, wherein said interconnect substrate feature comprises a plurality of interconnection lines for electrically coupling said first and second devices;
and a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system.

19 . The system of claim 18 , wherein said first substrate portion comprises a core and wherein said second substrate portion is a coreless substrate portion, and wherein said first height is greater than said second height, wherein the top portion of said first device is in level with the top portion of said second device.

20 . The system of claim 19 , wherein said second device is a memory stack comprising a plurality of memory devices, and wherein said first height and said second height are based upon the height of the memory stack.

Assignees

• Globalfoundries Inc

Inventors

• Mak Tak Ming

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/07254

  changes in dispositions · CPC title