Phase-change memory cell with mixed-material switchable region

Patent metadata

Field	Value
Publication number	US-12342736-B2
Application number	US-202218063189-A
Country	US
Kind code	B2
Filing date	Dec 8, 2022
Priority date	Dec 8, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

First claim

What is claimed is:

1. An electronic device comprising:
a first electrode;
a second electrode; and
a memory component configured to store a resistive state, the memory component including a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode, wherein:
the layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another,
the first material is a phase-change material and the second material is a non-phase-change material,
the bulk region is a continuous mass made of a third material that is different than the first material and the second material, and
the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

2. The electronic device of claim 1 , wherein:
the third material is a mixture of the first material and the second material.

3. The electronic device of claim 1 , wherein:
the bulk region is separated from the first electrode by the layered region.

4. The electronic device of claim 1 , wherein:
the layered region is separated from the second electrode by the bulk region.

5. The electronic device of claim 1 , wherein:
the bulk region includes a first lowermost surface arranged in direct contact with an uppermost surface of the second electrode,
the layered region includes a second lowermost surface arranged substantially coplanarly with the first lowermost surface.

6. The electronic device of claim 5 , wherein:
the first electrode includes a third lowermost surface arranged substantially coplanarly with the second lowermost surface.

7. The electronic device of claim 5 , wherein:
the first electrode includes a third lowermost surface separated from the second lowermost surface by a distance that is greater than zero.

8. The electronic device of claim 7 , wherein:
the third lowermost surface is substantially parallel to the uppermost surface.

9. The electronic device of claim 5 , wherein:
each first layer is in direct contact with a respective second layer at a respective planar interface surface such that each planar interface surface is separated by a first distance,
the bulk region extends a second distance in a direction substantially perpendicular to the planar interface surfaces, and
the second distance is greater than the first distance.

10. The electronic device of claim 9 , wherein:
each planar interface surface is substantially parallel to the uppermost surface.

11. The electronic device of claim 9 , wherein:
each planar interface surface is substantially perpendicular to the uppermost surface.

12. An electronic device comprising:
a first electrode having a lowermost surface;
a second electrode having an uppermost surface; and
a memory component configured to store a resistive state, the memory component including:
a layered region in direct contact with the first electrode, and
a bulk region arranged in direct contact with the uppermost surface of the second electrode, wherein:

the layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another,
the bulk region is a continuous mass made of a third material that is different than the first material and the second material,
the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region, and
the lowermost surface of the first electrode is substantially coplanar with the uppermost surface of the second electrode.

13. The electronic device of claim 12 , wherein:
at least one of the first material or the second material is a phase-change material.

14. The electronic device of claim 12 , wherein:
the third material is a mixture of the first material and the second material.

15. The electronic device of claim 12 , wherein:
the layered region is separated from the second electrode by the bulk region.

16. The electronic device of claim 12 , wherein:
the layered region has a further lowermost surface arranged substantially coplanarly with the lowermost surface of the first electrode.

17. An electronic device comprising:
a first electrode;
a second electrode having an uppermost surface; and
a memory component configured to store a resistive state, the memory component including a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the uppermost surface of the second electrode, wherein:
the layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another such that each first layer is in direct contact with a respective second layer at a respective planar interface surface,
the bulk region is a continuous mass made of a third material that is different than the first material and the second material,
the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region, and
each planar interface surface is substantially perpendicular to the uppermost surface.

18. The electronic device of claim 17 , wherein:
at least one of the first material or the second material is a phase-change material.

19. The electronic device of claim 17 , wherein:
the third material is a mixture of the first material and the second material.

20. The electronic device of claim 17 , wherein:
each planar interface surface is separated by a first distance,
the bulk region extends a second distance in a direction substantially perpendicular to the planar interface surfaces, and
the second distance is greater than the first distance.

Assignees

• IBM

Inventors

• Brightsky Matthew Joseph
• Cheng Cheng-Wei
• Cohen Guy M
• Bruce Robert L
• Ray Asit
• Kim Wanki

Classifications

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/821

  Device geometry · CPC title

• H10N70/253

  having three or more electrodes, e.g. transistor-like devices · CPC title

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title