Phase change memory devices including two-dimensional material and methods of operating the same

Patent metadata

Field	Value
Publication number	US-10217513-B2
Application number	US-201715448998-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Aug 23, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

First claim

What is claimed is:

1. A phase change memory device, comprising:
a first electrode;
a second electrode; and
a phase change layer between the first electrode and the second electrode, the phase change layer including a layered structure of at least one layer of two-dimensional (2D) material, the at least one layer of 2D material configured to at least partially change phase between a first crystalline phase and a second crystalline phase based on an electrical signal applied to the phase change layer through the first electrode and the second electrode, the second crystalline phase having a crystalline structure different from the first crystalline phase, none of the first and second crystalline phases being an amorphous phase.

2. The phase change memory device of claim 1 , wherein the 2D material includes a chalcogenide-based material.

3. The phase change memory device of claim 2 , wherein the chalcogenide-based material includes at least one of MoTe x , CoTe x , NbS x , SnS x , In x Se y , In—S, Tl—Se, Ge—Te, Ge—S, and Ge—Se.

4. The phase change memory device of claim 2 , wherein,
the chalcogenide-based material has a chemical formula unit of MG x , “M” is a metal element, “G” is a chalcogen element, and “x” satisfies about 1.5≤x<2.

5. The phase change memory device of claim 2 , wherein the 2D material includes a mixture of a first chalcogenide-based material and a second chalcogenide-based material.

6. The phase change memory device of claim 5 , wherein,
the first chalcogenide-based material is MoTe x ; and
the second chalcogenide-based material is WTe x .

7. The phase change memory device of claim 1 , wherein the 2D material includes phosphorene.

8. The phase change memory device of claim 1 , wherein,
the phase change layer further includes an intercalation material in the layered structure of the 2D material; and
the intercalation material includes Li.

9. The phase change memory device of claim 1 , wherein,
the phase change layer further includes a dopant, the dopant included in the 2D material; and
the dopant includes at least one of N, O, Si, and W.

10. The phase change memory device of claim 1 , wherein the 2D material is associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

11. The phase change memory device of claim 1 , wherein the phase change layer has a thickness that is equal to or less than about 50 nm.

12. The phase change memory device of claim 1 , wherein the at least one layer of 2D material includes a layer that extends substantially in parallel to a surface of a substrate.

13. The phase change memory device of claim 1 , wherein the at least one layer of 2D material includes a layer that extends substantially in perpendicular to a surface of a substrate.

14. The phase change memory device of claim 1 , wherein,
the first electrode includes a plug-type electrode portion;
the plug-type electrode portion has a width that is smaller than a width of the phase change layer; and
the plug-type electrode portion is in contact with the phase change layer.

15. The phase change memory device of claim 1 , wherein,
the phase change layer includes a plug portion;
the plug portion has a width that is smaller than a width of the first electrode; and
the plug portion is in contact with the first electrode.

16. The phase change memory device of claim 1 , further comprising:
a unit cell, the unit cell including the first electrode, the phase change layer, and the second electrode; and
a switching device electrically connected to the unit cell, the switching device including at least one of
a transistor,
a diode,
a threshold switch, and
a varistor.

17. The phase change memory device of claim 1 , wherein the phase change layer is configured to exhibit one or more multi-bit memory characteristics.

18. The phase change memory device of claim 17 , wherein
the phase change layer includes a multi-layer structure, the multi-layer structure including an alternating stack of a first material layer including the 2D material and a second material layer including a different material; and
the multi-layer structure is configured to exhibit the one or more multi-bit memory characteristics of the phase change layer.

19. The phase change memory device of claim 1 , wherein the phase change memory device is a stacked memory device, the stacked memory device including a plurality of memory devices stacked on a substrate.

20. A method of operating a phase change memory device, the method comprising:
applying a first electrical signal to a phase change layer for a first period of elapsed time, the phase change layer including a layered structure of at least one layer of two-dimensional (2D) material, to change a phase of at least a portion of the at least one layer of 2D material from a first crystalline phase to a second crystalline phase and to reduce a resistance of the phase change layer to cause the phase change layer to become a set state; and
applying a second electrical signal to the phase change layer for a second period of elapsed time to change the phase of at least the portion of the at least one layer of 2D material from the second crystalline phase to the first crystalline phase and to increase the resistance of the phase change layer to cause the phase change layer to become a reset state, the second period of elapsed time being longer than the first period of elapsed time.

21. The method of claim 20 , wherein,
the phase change layer is associated with a first phase change temperature and a second phase change temperature,
the first phase change temperature is a particular critical temperature associated with a phase change from the first crystalline phase into the second crystalline phase, such that the phase change layer is configured to change phase from the first crystalline phase to the second crystalline phase based on being at the first phase change temperature,
the second phase change temperature is a separate critical temperature associated with a phase change from the second crystalline phase into the first crystalline phase, such that the phase change layer is configured to change phase from the second crystalline phase to the first crystalline phase based on being at the second phase change temperature,
the first phase change temperature is greater than the second phase change temperature;
the applying of the first electrical signal includes cooling the 2D material after heating the 2D material to a first temperature that is greater than the first phase change temperature; and
the applying of the second electrical signal includes annealing the 2D material at a second temperature that is lower than the first phase change temperature and greater than the second phase change temperature.

22. The method of claim 21 , wherein the first temperature is lower than a melting temperature of the 2D material.

23. The method of claim 21 , wherein,
the first temperature is greater than a melting temperature of the 2D material; and
the second temperature is lower than the melting temperature of the 2D material.

24. The method of claim 21 , wherein,
the applying of the second electrical signal includes performing an initial heating operation and subsequently performing an annealing operation;
performing the initial heating operation includes heating the 2D material to at least a melting temperature of the 2D material

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minhyun
• Nam Seunggeol
• Kim Changhyun
• Shin Hyeonjin
• Cho Yeonchoo
• Heo Jinseong
• Park Seongjun

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H01L45/143

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic