Superlattice memory and crosspoint memory device

Patent metadata

Field	Value
Publication number	US-10026895-B2
Application number	US-201715427525-A
Country	US
Kind code	B2
Filing date	Feb 8, 2017
Priority date	Feb 9, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the superlattice structure portion, and a second layer provided on the other main surface of the superlattice structure portion in the deposition direction, which has a larger energy gap than that of the superlattice structure portion.

First claim

What is claimed is:

1. A memory device comprising:
a first electrode;
a first insulating film provided on the first electrode;
a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, the superlattice structure portion provided on the first insulating film;
a second insulating film provided on the superlattice structure portion; and
a second electrode provided on the second insulating film,
the first insulating film disposed between the first electrode and the superlattice structure portion,
the second insulating film disposed between the second electrode and the superlattice structure portion.

2. The device of claim 1 , wherein the first and second insulating films are SiO 2 , SiN or AlN.

3. The device of claim 1 , wherein the first chalcogen-compound layers are layered crystals each containing Sb, and the second chalcogen-compound layers are layered crystals each containing Ge.

4. The device of claim 1 , wherein the first chalcogen-compound layers are Sb 2 Te 3 layers, and the second chalcogen-compound layers are GeTe layers.

5. The device of claim 1 , wherein the superlattice structure portion and the first and second insulating films are shaped in to a pillar.

6. The device of claim 5 , wherein the superlattice structure portion and the first and second insulating films shaped into a pillar are provided in an interlayer insulating film.

7. The device of claim 1 , further comprising an interlayer insulating film provided on sides of the first insulating film, the superlattice structure portion, and the second insulating film.

8. A memory device comprising:
a plurality of first lines;
a plurality of second lines extending in a direction crossing the first lines;
superlattice memory cells respectively provided at intersections of the first lines and the second lines, the superlattice memory cells having superlattice structures containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited;
a first layer provided between one of main surfaces of each of the superlattice memory cells and one of the plurality of first lines and the plurality of second lines, the first layer being of a semiconductor or an insulator, which has a larger energy gap than that of the superlattice structure; and
a second layer provided between the other main surface of the each superlattice memory cell and the other of the plurality of first lines and the plurality of second lines, the second layer being a semiconductor or an insulator, which has a larger energy gap than that of the superlattice structure,
the one of main surfaces being a topmost main surface of each of the superlattice memory cells,
the other of main surfaces being bottommost main surface of each of the superlattice memory cells.

9. The device of claim 8 , wherein the first and second layers are each of SiO 2 , SiN, AlN or a high-k film.

10. The device of claim 8 , wherein the first chalcogen-compound layers are layered crystals each containing Sb, and the second chalcogen-compound layers are layered crystals each containing Ge.

11. The device of claim 8 , wherein the first chalcogen-compound layers are Sb 2 Te 3 layers, and the second chalcogen-compound layers are GeTe layers.

12. The device of claim 8 , wherein the first chalcogen-compound layers, the second chalcogen-compound layers and the first and second layers are shaped in to a pillar.

13. The device of claim 8 , wherein the first chalcogen-compound layers, the second chalcogen-compound layers and the first and second layers are provided to continuously extend in the superlattice memory cells.

14. The device of claim 8 , further comprising an interlayer insulating film provided on sides of the superlattice memory cells, the first layer, and the second layer.

Assignees

• Toshiba Kk

Inventors

• Kamata Yoshiki

Classifications

• H01L45/1253

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/144 Primary

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title