Dynamic logic built with stacked transistors sharing a common gate

Patent metadata

Field	Value
Publication number	US-2019355756-A1
Application number	US-201515774556-A
Country	US
Kind code	A1
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Nov 21, 2019
Grant date	—

Abstract

A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

First claim

1 . A dynamic logic circuit comprising:
a first transistor comprising a first semiconductor body within a first device stratum of a substrate; and a second transistor comprising a second semiconductor body within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode.

2 . The dynamic logic circuit of claim 1 , wherein the first transistor comprises a precharge transistor and the second transistor comprises an evaluate transistor.

3 . The dynamic logic circuit of claim 2 , wherein the first transistor comprises a P-type MOSFET.

4 . The dynamic logic circuit of claim 1 , wherein the first semiconductor body and the second transistor body each comprise a fin.

5 . The dynamic logic circuit of claim 1 , wherein the gate electrode wraps around the first semiconductor body and the second transistor body.

6 . The dynamic logic circuit of claim 1 , further comprising an inter-strata interconnect coupled to a drain of the first transistor and a drain of the second transistor.

7 . The dynamic logic circuit of claim 6 , wherein the inter-strata interconnect is coupled to an output line, the circuit further comprising an inverter cell coupled to the output line.

8 . The dynamic logic circuit of claim 7 , wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

9 . A dynamic logic circuit comprising:
a P-type MOSFET comprising a clock input; an N-type MOSFET logic circuit comprising one or more N-type MOSFETs comprising one or more logic inputs and an N-type MOSFET comprising the clock input; and an inverter cell coupled to the N-type logic circuit, wherein the P-type MOSFET is in a different device stratum of a substrate than the N-type MOSFET comprising the clock input and the P-type MOSFET and the N-type MOSFET comprising the clock input share a common gate electrode.

10 . The dynamic logic circuit of claim 9 , wherein a source of the P-type MOSFET is coupled to a power source.

11 . The dynamic logic circuit of claim 9 , further comprising an inter-stratum interconnect coupled to the drain of the P-type MOSFET and the drain of the N-type MOSFET comprising the clock input.

12 . The dynamic logic circuit of claim 11 , wherein the inter-stratum interconnect is coupled to an output line and the inverter cell is coupled to the output line.

13 . The dynamic logic circuit of claim 9 , wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

14 . The dynamic logic circuit of claim 13 , wherein the P-type MOSFET and the N-type MOSFET of the inverter cell are in different device strata on the substrate.

15 . A method comprising:
disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

16 . The method of claim 15 , wherein one of the first transistor and the second transistor comprises a P-type MOSFET and the other of the first transistor and the second transistor comprises an N-type MOSFET.

17 . The method of claim 16 , further comprising forming an inter-strata interconnect coupled to a drain of the first transistor and a drain of the second transistor.

18 . The method of claim 17 , wherein the inter-strata interconnect is coupled to an output line, the method further comprising forming an inverter cell coupled to the output line.

19 . The method of claim 18 , wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

20 . The method of claim 19 , wherein one of the P-type MOSFET and the N-type MOSFET of the inverter cell is formed in the first device stratum and the other of the P-type MOSFET and the N-type MOSFET of the inverter cell is formed in the second device stratum.

Assignees

• Intel Corp

Inventors

• Nelson Donald W
• Mehandru Rishabh

Classifications

• H03K19/0963

  using transistors of complementary type (H03K19/0966 takes precedence) · CPC title

• H01L21/823828

  Electricity · mapped topic

• H01L27/1211 Primary

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic