Lithographic cavity formation to enable EMIB bump pitch scaling

Patent metadata

Field	Value
Publication number	US-12334443-B2
Application number	US-202418434347-A
Country	US
Kind code	B2
Filing date	Feb 6, 2024
Priority date	Mar 23, 2018
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

First claim

What is claimed is:

1. An electronic package, comprising:
a first layer;
a second layer over the first layer;
a cavity through the second layer, the cavity including a first portion and a second portion above the first portion, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity, an uppermost surface of the second layer above an uppermost surface of the bridge substrate; and
a conductive pillar in the second layer, the conductive pillar laterally spaced apart from the bridge substrate.

2. An electronic package comprising:
a first layer;
a second layer over the first layer;
a cavity through the second layer, the cavity including a first portion and a second portion above the first portion, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity, a bottommost surface of the second layer at a same level as a bottommost surface of the bridge substrate; and
a conductive pillar in the second layer, the conductive pillar laterally spaced apart from the bridge substrate.

3. The electronic package of claim 1 , wherein the conductive pillar has an uppermost surface above the uppermost surface of the bridge substrate.

4. The electronic package of claim 1 , wherein the conductive pillar has a bottommost surface at a same level as a bottommost surface of the bridge substrate.

5. The electronic package of claim 1 , including a first die above and coupled to the bridge substrate.

6. The electronic package of claim 5 , wherein the first die is coupled to the conductive pillar.

7. The electronic package of claim 5 , including a second die above and coupled to the bridge substrate, the second die laterally spaced apart from the first die.

8. An electronic package comprising:
a first layer;
a second layer over the first layer;
a cavity through the second layer, the cavity including a first portion and a second portion above the first portion, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity;
a conductive pillar in the second layer, the conductive pillar laterally spaced apart from the bridge substrate; and
a third layer, the third layer fills the cavity and is over a top surface of the second layer and over a top surface of the bridge substrate.

9. The electronic package of claim 8 , including:
a first conductive via in the third layer, the first conductive via coupled to the bridge substrate; and
a second conductive via in the third layer, the second conductive via coupled to the conductive pillar.

10. An electronic package, comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer;
a cavity through the second layer and the third layer, wherein the cavity includes a first portion in the third layer, and a second portion below the first portion, the second portion in the second layer, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity, an uppermost surface of the third layer above an uppermost surface of the bridge substrate; and
a conductive pillar in the second layer and the third layer, the conductive pillar laterally spaced apart from the bridge substrate.

11. An electronic package comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer;
a cavity through the second layer and the third layer, wherein the cavity includes a first portion in the third layer, and a second portion below the first portion, the second portion in the second layer, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity, a bottommost surface of the second layer at a same level as a bottommost surface of the bridge substrate; and
a conductive pillar in the second layer and the third layer, the conductive pillar laterally spaced apart from the bridge substrate.

12. An electronic package comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer;
a cavity through the second layer and the third layer, wherein the cavity includes a first portion in the third layer, and a second portion below the first portion, the second portion in the second layer, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity; and
a conductive pillar in the second layer and the third layer, the conductive pillar laterally spaced apart from the bridge substrate, an uppermost surface of the conductive pillar above an uppermost surface of the bridge substrate.

13. An electronic package comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer;
a cavity through the second layer and the third layer, wherein the cavity includes a first portion in the third layer, and a second portion below the first portion, the second portion in the second layer, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity; and
a conductive pillar in the second layer and the third layer, the conductive pillar laterally spaced apart from the bridge substrate, a bottommost surface of the conductive pillar at a same level as a bottommost surface of the bridge substrate.

14. The electronic package of claim 10 , including a first die above and coupled to the bridge substrate.

15. The electronic package of claim 14 , wherein the first die is coupled to the conductive pillar.

16. The electronic package of claim 14 , including a second die above and coupled to the bridge substrate, the second die laterally spaced apart from the first die.

17. An electronic package comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer;
a cavity through the second layer and the third layer, wherein the cavity includes a first portion in the third layer, and a second portion below the first portion, the second portion in the second layer, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity:
a conductive pillar in the second layer and the third layer, the conductive pillar laterally spaced apart from the bridge substrate; and
a fourth layer, wherein the fourth layer fills the cavity and is over a top surface of the third layer and over a top surface of the bridge substrate.

18. The electronic package of claim 17 , including:
a first conductive via in the fourth layer, the first conductive via coupled to the bridge substrate; and
a second conductive via in the fourth layer, the second conductive via coupled to the conductive pillar.

Assignees

• Intel Corp

Inventors

• Darmawikarta Kristof
• Tanaka Hiroki
• May Robert
• Paital Sameer
• Nie Bai
• Jones Jesse
• Tan Chung Kwang Christopher

Classifications

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title