Non-linear polar material based multi-capacitor high density bit-cell

Patent metadata

Field	Value
Publication number	US-12334127-B2
Application number	US-202318161808-A
Country	US
Kind code	B2
Filing date	Jan 30, 2023
Priority date	Jan 30, 2023
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

First claim

We claim:

1. An apparatus comprising:
a plurality of capacitors, wherein an individual capacitor of the plurality of capacitors is coupled to a node and an individual plate-line;
a first transistor coupled to the node;
a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a sense-line; and
a third transistor coupled to the node and a bit-line, wherein the third transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

2. The apparatus of claim 1 , wherein the second transistor is controllable to reduce leakage through the node to the sense-line.

3. The apparatus of claim 1 , wherein the second transistor is controllable by the word-line.

4. The apparatus of claim 1 , wherein the first transistor is smaller in size than the second transistor.

5. The apparatus of claim 1 , wherein the second transistor is controllable by a read word-line separate from the word-line.

6. The apparatus of claim 1 , wherein the individual capacitor comprises a non-linear polar material.

7. The apparatus of claim 6 , wherein the non-linear polar material is directly on the node.

8. The apparatus of claim 6 , wherein the non-linear polar material is one of a ferroelectric material, a paraelectric material, or a non-linear dielectric material.

9. The apparatus of claim 6 , wherein the non-linear polar material is doped with one or more elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of a periodic table.

10. The apparatus of claim 6 , wherein the non-linear polar material includes one of:
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO);
barium titanate (BTO);
BFO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
BTO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
LBFO doped with Mn;
lead zirconium titanate (PZT) or PZT with a first doping material, wherein the first doping material is one of La, Nb, Mn, or 5d series elements;
bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of the periodic table;
a relaxor ferroelectric material which includes one of; lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides;
hafnium oxides as Hf (1-x) E x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100, or a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or PMN-PT based relaxor ferroelectrics; or
a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or PMN-PT based relaxor ferroelectrics.

11. The apparatus of claim 1 , wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and/or folded configuration.

12. The apparatus of claim 1 , wherein the bit-line is orthogonal to the word-line and the individual plate-line.

13. An apparatus comprising:
a plurality of capacitors, wherein an individual capacitor of the plurality of capacitors is coupled to a node and an individual plate-line;
a first transistor having a first gate terminal coupled to the node, and a first drain terminal coupled to a reference;
a second transistor coupled in series with the first transistor such that a first source terminal of the first transistor is coupled to a second drain terminal of the second transistor, wherein a second source terminal of the second transistor is coupled to a sense-line; and
a third transistor having a third source terminal coupled to a bit-line, a third drain terminal coupled the node, and a third gate terminal coupled to a word-line.

14. The apparatus of claim 13 , wherein the word-line is parallel to the individual plate-line, wherein the word-line is orthogonal to the bit-line.

15. The apparatus of claim 13 , wherein the second transistor has a second gate terminal which is controllable by the word-line, or wherein the second gate terminal is controllable by a read word-line.

16. The apparatus of claim 13 , wherein the second transistor is controllable to reduce leakage through the node to the sense-line.

17. The apparatus of claim 13 , wherein the second transistor is smaller in size than the first transistor.

18. The apparatus of claim 13 , wherein the individual capacitor comprises a non-linear polar material.

19. The apparatus of claim 18 , wherein the non-linear polar material is directly on the node.

20. A system comprising:
a memory to store instructions;
a processor circuitry to execute the instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
a plurality of capacitors, wherein an individual capacitor of the plurality of capacitors is coupled to a node and an individual plate-line;
a first transistor having a first drain terminal coupled to a reference;
a second transistor coupled in series with the first transistor such that a first source terminal of the first transistor is coupled to a second drain terminal of the second transistor, wherein a second source terminal of the second transistor is coupled to a sense-line, and wherein the second transistor has a gate terminal coupled to the node; and
a third transistor having a third source terminal coupled to a bit-line, a third drain terminal coupled the node, and a third gate terminal coupled to a word-line.

Assignees

• Kepler Computing Inc

Inventors

• Dokania Rajeev Kumar
• Mukadam Mustansir Yunus
• Unterborn Erik
• Kolar Pramod
• Mathuriya Amrita
• Olaosebikan Debo
• Gosavi Tanay
• Sato Noriyuki
• Manipatruni Sasikanth

Classifications

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2259

  Cell access · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title