Dynamic adjustment of memory cell digit line capacitance

Patent metadata

Field	Value
Publication number	US-9786348-B1
Application number	US-201615095962-A
Country	US
Kind code	B1
Filing date	Apr 11, 2016
Priority date	Apr 11, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

First claim

What is claimed is:

1. A method of operating a ferroelectric memory array, comprising:
shorting a first digit line of a first ferroelectric memory cell with a second digit line of a second ferroelectric memory cell;
activating a selection component that is in electronic communication with the first digit line of the first ferroelectric memory cell based at least in part on shorting the first digit line with the second digit line;
determining that a voltage of the first digit line has reached a threshold value; and
isolating the first digit line from the second digit line based at least in part on activating the selection component and the determination that the voltage of the first digit line has reached the threshold value.

2. The method of claim 1 , further comprising:
activating a sense component that is in electronic communication with the first digit line within a threshold time after isolating the first digit line from the second digit line.

3. The method of claim 1 , wherein shorting the first digit line with the second digit line comprises:
activating a switching device that is in electronic communication with the first digit line and the second digit line.

4. The method of claim 1 , wherein the second ferroelectric memory cell comprises an inactive memory cell of the ferroelectric memory array.

5. The method of claim 1 , further comprising:
applying a voltage to a plate of the first ferroelectric memory cell after shorting the first digit line with the second digit line and prior to isolating the first digit line from the second digit line.

6. The method of claim 1 , further comprising:
determining that a threshold amount of time has elapsed since the activation of the selection component, wherein the isolation is based at least in part on the determination that the threshold amount of time has elapsed.

7. The method of claim 1 , further comprising:
initializing the first digit line and the second digit line to a same voltage, wherein shorting the first digit line with the second digit line occurs after the initialization.

8. A method of operating a ferroelectric memory cell, comprising:
dynamically increasing a capacitance of a digit line of the ferroelectric memory cell;
applying a voltage to a word line of the ferroelectric memory cell based at least in part on increasing the capacitance;
determining that a voltage of the digit line has reached a threshold value; and
reducing the capacitance of the digit line based at least in part on applying the voltage to the word line and the determination that the voltage of the digit line has reached the threshold value.

9. The method of claim 8 , wherein dynamically increasing the capacitance comprises:
shorting the digit line of the ferroelectric memory cell with a digit line of another ferroelectric memory cell.

10. The method of claim 9 , further comprising:
initializing the digit lines of the ferroelectric memory cells to a same voltage before increasing the capacitance.

11. The method of claim 8 , wherein dynamically increasing the capacitance comprises:
establishing a connection between the digit line of the ferroelectric memory cell and a capacitor.

12. The method of claim 8 , further comprising:
applying a voltage to a ferroelectric capacitor of the ferroelectric memory cell after increasing the capacitance of the digit line, wherein the capacitance of the digit line is reduced after the application of the voltage to the ferroelectric capacitor.

13. The method of claim 12 , further comprising:
activating a sense component that is in electronic communication with the digit line while the voltage is applied to the ferroelectric capacitor.

14. The method of claim 12 , further comprising:
transferring charge from the ferroelectric memory cell to the digit line based at least in part on the application of the voltage to the ferroelectric memory cell.

15. The method of claim 14 , further comprising:
determining that a voltage of the digit line resulting from the transfer of charge satisfies a second threshold value, wherein reducing the capacitance of the digit line is based at least in part on the determination that the second threshold value is satisfied.

16. The method of claim 8 , further comprising:
determining that a threshold amount of time has expired since applying the voltage to the word line, wherein reducing the capacitance is based at least in part on the determination that the threshold amount of time has expired.

17. An electronic memory apparatus, comprising:
a first ferroelectric memory cell in electronic communication with a first digit line;
a switching component in electronic communication with the first digit line and a second digit line of a second ferroelectric memory cell; and
a controller in electronic communication with the first ferroelectric memory cell and the switching component, wherein the controller is operable to:
activate the switching component;
activate a selection component of the first ferroelectric memory cell based at least in part on activation of the switching component;
determining that a voltage of the first digit line has reached a threshold value; and
deactivate the switching component based at least in part on activation of the selection component and the determination that the voltage of the first digit line has reached the threshold value.

18. The electronic memory apparatus of claim 17 , further comprising:
a sense component in electronic communication with the first digit line and the controller, wherein the controller is operable to:
activate the sense component after deactivation of the switching component.

19. The electronic memory apparatus of claim 17 , wherein the controller is operable to:
determine that a voltage is applied to a plate of the first ferroelectric memory cell, wherein deactivation of the switching component is based at least in part on a determination that the voltage is applied to the plate.

Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher
• Ingalls Charles
• Derner Scott

Classifications

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2259

  Cell access · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title