Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12328937-B2
Application number	US-202318120547-A
Country	US
Kind code	B2
Filing date	Mar 13, 2023
Priority date	Oct 22, 2019
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first fin-type active area arranged on a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material;
a second fin-type active area arranged on the substrate, spaced apart from the first fin-type active area in a second direction perpendicular to the first direction, wherein the second fin-type active area extends in the first direction, includes the first semiconductor material, and has a first sidewall facing the first fin-type active area and a second sidewall opposite to the first sidewall;
a first capping layer that surrounds an upper surface and a sidewall of the first fin-type active area, the first capping layer including a second semiconductor material that is different from the first semiconductor material, and the first capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall;
a second capping layer that surrounds an upper surface and the first and second sidewalls of the second fin-type active area, the second capping layer including the second semiconductor material, the second capping layer comprising a first portion arranged on the first sidewall of the second fin-type active area, and a second portion arranged on the second sidewall of the second fin-type active area and having a bottom surface arranged at a higher level than a bottom surface of the first portion; and
a gate structure that crosses the first fin-type active area and the second fin-type active area and extends in the second direction.

2. The integrated circuit device of claim 1 , further comprising:
an isolation layer that surrounds both sidewalls of the first fin-type active area and the first and second sidewalls of the second fin-type active area, the isolating layer including an insulation liner and an insulation filling layer, and having a bottom surface arranged at a first level; and
a deep trench isolation layer that surrounds the isolation layer when viewed in a plan view and has a bottom surface that is arranged at a second level that is closer to the upper surface of the substrate than the first level is to the upper surface of the substrate.

3. The integrated circuit device of claim 2 , wherein an upper surface level of a portion of the insulation liner arranged on the first sidewall of the second fin-type active area is closer to the upper surface of the substrate than an upper surface level of a portion of the insulation liner arranged on the second sidewall of the second fin-type active area is to the upper surface of the substrate.

4. The integrated circuit device of claim 2 , wherein the first portion of the second capping layer is arranged on a portion of the first sidewall of the second fin-type active area that is not covered by the insulation liner, and
wherein the second portion of the second capping layer is arranged on a portion of the second sidewall of the second fin-type active area that is not covered by the insulation liner.

5. The integrated circuit device of claim 2 , wherein an upper surface of a portion of the isolation layer that surrounds the first sidewall of the second fin-type active area is arranged closer to the upper surface of the substrate than an upper surface of a portion of the isolation layer that surrounds the second sidewall of the second fin-type active area is to the upper surface of the substrate.

6. The integrated circuit device of claim 1 , wherein the first capping layer has a first thickness on the upper surface of the first fin-type active area, and
wherein the first capping layer has a second thickness at an edge of the facet surface, the second thickness being less than the first thickness.

7. The integrated circuit device of claim 6 , wherein the first thickness is between about 5 Å to about 30 Å.

8. The integrated circuit device of claim 1 , wherein the first semiconductor material includes silicon germanium and the second semiconductor material includes silicon.

9. An integrated circuit device comprising:
a first fin-type active area arranged on a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material;
a second fin-type active area arranged on the substrate, spaced apart from the first fin-type active area in a second direction perpendicular to the first direction, wherein the second fin-type active area extends in the first direction, includes the first semiconductor material, and has a first sidewall facing the first fin-type active area and a second sidewall opposite to the first sidewall;
a first capping layer that surrounds an upper surface and a sidewall of the first fin-type active area, the first capping layer including a second semiconductor material that is different from the first semiconductor material, and the first capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall;
a second capping layer that surrounds an upper surface and the first and second sidewalls of the second fin-type active area and includes the second semiconductor material, the second capping layer comprising a first portion arranged on the first sidewall of the second fin-type active area, and a second portion arranged on the second sidewall of the second fin-type active area and having a bottom surface arranged at a higher level than a bottom surface of the first portion; and
a gate structure that crosses both the first fin-type active area and the second fin-type active area and extends in the second direction,
wherein at least one of the first fin-type active area and the second fin-type active area includes a surface area and an inside area that is covered by the surface area,
wherein the surface area has a first germanium content and the inside area has a second germanium content that is less than the first germanium content.

10. The integrated circuit device of claim 9 ,
wherein the surface area has a first bandgap energy,
wherein the inside area has a second bandgap energy, and
wherein the second bandgap energy is greater than the first bandgap energy.

11. The integrated circuit device of claim 10 ,
wherein the first capping layer has a third bandgap energy, and
wherein the third bandgap energy is greater than the second bandgap energy.

12. The integrated circuit device of claim 9 , further comprising:
an isolation layer that surrounds both sidewalls of the first fin-type active area and the first and second sidewalls of the second fin-type active area, the isolation layer including an insulation liner and an insulation filling layer, and having a bottom surface arranged at a first level; and
a deep trench isolation layer that surrounds the isolation layer when viewed in a plan view and has a bottom surface arranged at a second level that is closer to the upper surface of the substrate than the first level is to the upper surface of the substrate.

13. The integrated circuit device of claim 12 , wherein an upper surface level of a portion of the insulation liner arranged on the first sidewall of the second fin-type active area is closer to the upper surface of the substrate than an upper surface level of a portion of the insulation liner arranged on the second sidewall of the second fin-type active area is to the upper surface of the substrate.

14. The integrated circuit device of claim 12 , wherein the first portion of the second capping layer is arranged on a portion of the first sidewall of the second fin-type active area that is not covered by the insulati

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaemun
• Kim Gyeom
• Kim Dahye
• Kim Jinbum
• Choi Kyungin
• Shin Ilgyou
• Lee Seunghun

Classifications

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title