Semiconductor Fin FET device with epitaxial source/drain

Patent metadata

Field	Value
Publication number	US-10312369-B2
Application number	US-201715837826-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	Sep 4, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively;
a contact layer disposed over the first and second strain material layers; and
an insulating layer separating the gate structure and the contact layer,
wherein the first strain material layer is separated from the second strain material layer,
wherein the first and second fin structures further include mask layers under the insulating layer and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

2. The semiconductor device of claim 1 , wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

3. The semiconductor device of claim 1 , wherein the first and second strained material layers are selectively grown over the first and second source/drain regions, respectively, to cover surface of sidewalls and top surface of the first and second source/drain regions along different crystal orientations including <100>, <110>, and <101>.

4. The semiconductor device of claim 1 , further comprising an interconnect layer filling an opening over the contact layer.

5. The semiconductor device of claim 4 , wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

6. The semiconductor device of claim 4 , wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

7. The semiconductor device of claim 1 , wherein a width of the first source/drain region is 40% to 60% of a width of the first channel.

8. A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively;
a contact layer disposed over the first and second strain material layers; and
an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer, respectively, and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

9. The semiconductor device of claim 8 , wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

10. The semiconductor device of claim 8 , further comprising an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

11. The semiconductor device of claim 8 , wherein the first and second strained material layers are selectively grown over the first and second source/drain regions, respectively, to cover surface of sidewalls and top surface of the first and second source/drain regions along different crystal orientations including <100>, <110>, and <101>.

12. The semiconductor device of claim 8 , further comprising an interconnect layer filling in an opening over the contact layer.

13. The semiconductor device of claim 12 , wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

14. The semiconductor device of claim 12 , wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

15. The semiconductor device of claim 8 , wherein a width of the first source/drain region is 40% to 60% of a width of the first channel.

16. A semiconductor device, comprising:
a substrate;
a fin structure disposed over the substrate and including a channel region and a source/drain region;
a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure;
a strain material layer disposed over the source/drain region, the strain material layer providing stress to the channel region;
a contact layer disposed over the strain material layer; and
an insulating layer separating the gate structure and the contact layer,
wherein the fin structure further includes a mask layer under the insulating layer and does not have the mask layer in the channel region and the source/drain region.

17. The semiconductor device of claim 16 , further comprising an interconnect layer filling in an opening over the contact layer.

18. The semiconductor device of claim 17 , wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

19. The semiconductor device of claim 17 , wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

20. The semiconductor device of claim 16 , wherein a width of the source/drain region is 40% to 60% of a width of the channel.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Hung-Li
• Peng Cheng-Yi
• Sheu Jyh-Cherng
• Yeo Yee-Chia

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/26586

  Electricity · mapped topic