Spacer structure for semiconductor device

Patent metadata

Field	Value
Publication number	US-12324209-B2
Application number	US-202318309433-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Aug 11, 2020
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.

First claim

What is claimed is:

1. A structure, comprising:
channel regions over a substrate;
a gate structure surrounding the channel regions;
a source/drain (S/D) structure adjacent to the channel regions; and
an inner spacer structure between the channel regions and separating the gate structure and the S/D structure, comprising:
a first inner spacer, wherein a front surface of the first inner spacer is in contact with the gate structure; and
a second inner spacer in contact with the gate structure and the front surface of the first inner spacer.

2. The structure of claim 1 , wherein the inner spacer structure further comprises a third inner spacer in contact with the S/D structure and the first inner spacer.

3. The structure of claim 1 , wherein the first inner spacer comprises a dielectric material free from carbon.

4. The structure of claim 1 , wherein the second inner spacer comprises a carbon-contained oxide material.

5. The structure of claim 1 , wherein the second inner spacer is in contact with a side surface of the first inner spacer.

6. The structure of claim 1 , wherein the second inner spacer is in contact with a curved portion of the front surface of the first inner spacer.

7. The structure of claim 1 , wherein the front surface of the first inner spacer comprises a flat portion and a curved portion.

8. A structure, comprising:
channel regions over a substrate;
a gate structure surrounding the channel regions;
a source/drain (S/D) structure adjacent to the channel regions; and
an inner spacer structure between the channel regions, comprising:
a first inner spacer comprising a first surface in contact with the gate structure and a second surface in contact with the S/D structure; and
a second inner spacer having dielectric surfaces in contact with the S/D structure and a third surface of the first inner spacer.

9. The structure of claim 8 , wherein oxide concentrations of the first and second inner spacers are different.

10. The structure of claim 8 , further comprising a gate spacer formed between the gate structure and the S/D structure, wherein the gate spacer is separated from the first inner spacer by the second inner spacer.

11. The structure of claim 8 , wherein the inner spacer structure further comprises a third inner spacer in contact with the gate structure and a curved portion of the first surface of the first inner spacer.

12. The structure of claim 11 , wherein a surface of the second inner spacer and a surface of the third inner spacer are coplanar.

13. The structure of claim 8 , wherein the third surface is perpendicular to the first and second surfaces.

14. The structure of claim 8 , wherein the first inner spacer comprises a dielectric material free from carbon.

15. A structure, comprising:
a vertical stack over a substrate, the vertical stack comprising:
a plurality of nano-sheet layers;
a gate structure surrounding the plurality of nano-sheet layers; and
an inner spacer structure adjacent to the gate structure and comprising:
a first inner spacer in contact with the gate structure on an interface; and
a second inner spacer surrounding the interface from a top view; and

a source/drain (S/D) structure adjacent to the plurality of nano-sheet layers and the inner spacer structure.

16. The structure of claim 15 , wherein:
the first inner spacer comprises a dielectric material free from carbon; and
the second inner spacer comprises a carbon-contained oxide material.

17. The structure of claim 15 , wherein the inner spacer structure further comprises a third inner spacer in contact with the S/D structure, the first inner spacer, and the second inner spacer.

18. The structure of claim 17 , wherein oxide concentrations of the first and third inner spacers are different.

19. The structure of claim 15 , wherein the inner spacer structure further comprises a gate spacer separating the gate structure and the S/D structure, wherein the gate spacer is separated from the first inner spacer by the second inner spacer.

20. The structure of claim 15 , wherein the interface comprises a curved surface.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title