Spacer structure for semiconductor device

Patent metadata

Field	Value
Publication number	US-11289586-B2
Application number	US-202016990865-A
Country	US
Kind code	B2
Filing date	Aug 11, 2020
Priority date	Aug 11, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
channel regions over the substrate;
a gate structure over the channel regions;
an inner spacer layer formed between the channel regions and in contact with the gate structure; and
an other inner spacer layer extending through the inner spacer layer, wherein a front surface of the other inner spacer layer is in contact with the inner spacer layer.

2. The semiconductor structure of claim 1 , wherein the other inner spacer layer is in contact with the gate structure.

3. The semiconductor structure of claim 1 , wherein the inner spacer layer and the other inner spacer layer are substantially coplanar with the gate structure.

4. The semiconductor structure of claim 1 , wherein the other inner spacer layer comprises the front surface and a side surface, wherein the front surface is in contact with the gate structure, and wherein the side surface is substantially perpendicular to the substrate and in contact with the inner spacer layer.

5. The semiconductor structure of claim 1 , wherein the inner spacer layer comprises first and second dielectric layers.

6. The semiconductor structure of claim 5 , wherein the first dielectric layer is in contact with the gate structure and the second dielectric layer is separated from the gate structure.

7. The semiconductor structure of claim 1 , further comprising a gate spacer layer in contact with the inner spacer layer, wherein the gate spacer layer is separated from the other inner spacer layer.

8. The semiconductor structure of claim 1 , wherein the inner spacer layer and the other inner spacer layer are in contact with the channel regions.

9. A semiconductor structure, comprising:
a substrate;
channel regions over the substrate;
a gate structure formed over the channel regions;
a source/drain (S/D) region formed adjacent to the channel regions and separated from the gate structure;
an inner spacer layer formed between the channel regions and adjacent to the gate structure; and
an other inner spacer layer extending from the gate structure to the S/D region and comprising a side surface substantially perpendicular to the substrate, wherein the inner spacer layer is over the side surface of the other inner spacer layer.

10. The semiconductor structure of claim 9 , wherein the inner spacer layer and the other inner spacer layer are in contact with the gate structure.

11. The semiconductor structure of claim 9 , wherein the inner spacer layer and the other inner spacer layer are substantially coplanar with the gate structure.

12. The semiconductor structure of claim 9 , wherein a front surface of the other inner spacer layer is in contact with the gate structure and the inner spacer layer.

13. The semiconductor structure of claim 9 , wherein the inner spacer layer comprises first and second dielectric layers.

14. The semiconductor structure of claim 13 , wherein the first dielectric layer is in contact with the gate structure and the second dielectric layer is in contact with the S/D region.

15. A method, comprising:
forming channel regions over a substrate;
forming a first recess structure adjacent to the channel regions to expose a side surface of the channel regions;
forming a first inner spacer layer protruding into the side surface of the channel regions;
forming a second recess structure between the channel regions to expose a side surface of the first inner spacer layer, wherein the side surface of the first inner spacer layer is substantially perpendicular to the substrate; and
forming a second inner spacer layer over the side surface of the first inner spacer layer.

16. The method of claim 15 , wherein forming the second recess structure comprises performing a radical etching process to remove a portion of a sacrificial layer between the channel regions.

17. The method of claim 15 , wherein forming the second inner spacer layer comprises performing a radical deposition process to deposit a dielectric layer over the side surface of the first inner spacer layer.

18. The method of claim 15 , wherein forming the second recess structure and forming the second inner spacer layer comprise generating a radical via a radical source to etch a sacrificial layer between the channel regions.

19. The method of claim 18 , wherein forming the second recess structure comprises moving the substrate towards the radical source, and wherein forming the second inner spacer layer comprises moving the substrate away from the radical source.

20. The method of claim 15 , further comprising forming a source/drain (S/D) epitaxial region in the first recess structure, wherein forming the first inner spacer layer comprises depositing a first dielectric layer before forming the S/D epitaxial region, and wherein forming the second inner spacer layer comprises depositing a second dielectric layer after forming the S/D epitaxial region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title