Hybrid solid state drive (SSD) architecture using MRAM and NAND for improved power loss protection and performance

Patent metadata

Field	Value
Publication number	US-12321639-B2
Application number	US-202318309825-A
Country	US
Kind code	B2
Filing date	Apr 30, 2023
Priority date	Oct 10, 2022
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

An SSD includes an MRAM, an NAND memory, and an SSD controller. The SSD controller is configured to receive first data from a host machine, save the first data to an SSD data buffer, fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller, determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory, and in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM.

First claim

What is claimed is:

1. A solid state drive (SSD) comprising:
a magnetoresistive random-access memory (MRAM);
a NAND memory; and
an SSD controller coupled to the MRAM and the NAND memory, wherein the SSD controller comprises:
a data allocation circuit configured to determine saving data to one of the MRAM or the NAND memory; and
an MRAM controller coupled to the MRAM and configured to read data from or write data to the MRAM,

wherein the SSD controller is configured to:
receive first data from a host machine;
save the first data to an SSD data buffer;
fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller;
determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory;
in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM,
wherein the data allocation circuit is further configured to:
calculate a read access frequence of a logic block in the NAND memory,
determine whether the read access frequency of the logic block exceeds a threshold frequency determined based on a storage capacity of the MRAM, wherein the threshold frequency is inversely related to the storage capacity of the MRAM, and
in response to determining the read access frequency of the logic block exceeding the threshold frequency, relocate data stored on the logic block on the NAND memory to the MRAM.

2. The SSD of claim 1 , wherein the SSD controller is configured to:
in response to determining saving the first data to the MRAM, retain the first data at the MRAM.

3. The SSD of claim 2 , wherein the SSD controller is further configured to record in an addressing table a physical address of the first data at the MRAM or the NAND memory.

4. The SSD of claim 3 , wherein the SSD controller is further configured to save the addressing table at the MRAM or a dynamic random-access memory (DRAM) coupled to the SSD controller.

5. The SSD of claim 3 , wherein the SSD controller is further configured to:
receive a read command from the host machine for reading second data;
look up, by the data allocation circuit, the addressing table to determine whether the second data are saved at the MRAM or the NAND memory;
in response to determining that the second data are saved at the MRAM, fetch the second data from the MRAM and save the second data to the SSD data buffer;
in response to determining that the second data are saved at the NAND memory, fetch the second data from the NAND memory and save the second data to the SSD data buffer; and
fetch the second data from the SSD data buffer and send the second data to the host machine.

6. The SSD of claim 5 , wherein the SSD controller is further configured to:
determine whether a number of read access from the host machine to the second data over a time duration exceeds a threshold;
in response to that the number of read access to the second data over the time duration from the host machine exceeds the threshold and in response to determining that the second data are saved at the NAND memory, relocate the second data from the NAND memory to the MRAM, erase the second data from the NAND memory, and update a physical address of the second data in the addressing table.

7. The SSD of claim 1 , wherein the data allocation circuit is further configured to:
calculate a read access frequency of each logic block on the MRAM;
determining whether the read access frequency of each logic block on the MRAM exceeds the threshold frequency; and
in response to determining that a read access frequency of a logic block on the MRAM does not exceed the threshold frequency, relocate data stored at the logic block on the MRAM to the NAND memory.

8. The SSD of claim 1 , wherein the data allocation circuit comprises a machine learning model, the machine learning model comprises a data allocation engine and a data relocation engine, and is configured to, in response to receiving a read command from the host machine for reading second data stored on the SSD:
calculate a read access frequency of the second data;
obtain a current state of the machine learning model;
input the read access frequency of the second data and the current state of the machine learning model into the data allocation engine for the data allocation engine to determine whether the second data are to be saved on the MRAM or the NAND memory and to generate a determination result;
input the determination result of the data allocation engine into the data relocation engine for the data relocation engine to determine whether to relocate the second data between the MRAM and the NAND memory;
calculate a read access latency for accessing the second data stored on the SSD; and
generate a machine learning sample comprising the read access frequency of the second data, the current state of the machine learning model, an output of the data relocation engine, and the read access latency.

9. The SSD of claim 1 , wherein the SSD controller is further configured to flush, in response to a power loss, all data at the SSD data buffer to the MRAM.

10. An apparatus comprising a host machine and a solid state drive (SSD), wherein the SSD comprises:
a magnetoresistive random-access memory (MRAM);
a NAND memory; and
an SSD controller coupled to the MRAM and the NAND memory, wherein the SSD controller comprises:
a data allocation circuit configured to determine saving data to one of the MRAM or the NAND memory; and
an MRAM controller coupled to the MRAM and configured to read data from or write data to the MRAM,

wherein the SSD controller is configured to:
receive first data from a host machine;
save the first data to an SSD data buffer;
fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller;
determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory;
in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM,
wherein the data allocation circuit is further configured to:
calculate a read access frequence of a logic block in the NAND memory,
determine whether the read access frequency of the logic block exceeds a threshold frequency determined based on a storage capacity of the MRAM, wherein the threshold frequency is inversely related to the storage capacity of the MRAM, and
in response to determining the read access frequency of the logic block exceeding the threshold frequency, relocate data stored on the logic block on the NAND memory to the MRAM.

11. The apparatus of claim 10 , wherein the SSD controller is configured to:
in response to determining saving the first data to the MRAM, retain the first data at the MRAM.

12. The apparatus of claim 11 , wherein the SSD controller is further configured to record in an addressing table a physical address of the first data at the MRAM or the NAND memory.

13. The apparatus of claim 12 , wherein the SSD controller is further configured to save the addressing table at the MRAM or a dynamic random-access memory (DRAM) coupled to the SSD controller.

14. The apparatus of claim 12 , wherein the SSD controller is further configured to:
receive a read command from the host machine for reading second data;
look up, by the data allocation circuit, the addressing table to determine whethe

Assignees

• Alibaba China Co Ltd

Inventors

• Xue Fei
• Wu Wentao
• Jin Jiajing
• Gao Xiang
• Wang Jifeng
• Xu Yuming
• Heng Jiu
• Zheng Hongzhong

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0607

  by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title