Parity generating information processing system

US10853268B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10853268-B2
Application numberUS-201616081876-A
CountryUS
Kind codeB2
Filing dateJun 15, 2016
Priority dateJun 15, 2016
Publication dateDec 1, 2020
Grant dateDec 1, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An information processing system including a processor, a memory, and a plurality of drives, wherein when a write request of new data is received, the processor stores the new data in the memory, transmits a response for the write request to a transmission source of the write request, reads old data updated by the new data from a first drive of the plurality of drives and old parity related to the old data from a second drive of the plurality of drives according to transmission of the response, store the old data and the old parity in the memory, generates new parity related to the new data from the new data, the old data, and the old parity stored in the memory, and stores the new data in the first drive to store the new parity in the second drive.

First claim

Opening claim text (preview).

The invention claimed is: 1. An information processing system including a processor and a memory and performing data input/output with respect to a storage device, wherein the memory includes a buffer area and a cache area, the processor is configured to perform a write process, the write process includes storing new data associated with a received write request in the memory, reading old data updated by the new data and an old parity according to the old data from the storage device, storing the old data and the old parity in the memory, generating, based on the new data, the old data, and the old parity, a new parity according to the new data, storing the new parity in the memory, and storing the new data and the new parity in the storage device, wherein the processor is further configured to perform a first write process where the new data is to be stored in the buffer area or a second write process where the new data is to be stored in the cache area, and when receiving a read request of the new data while the first write process is in progress, the processor performs the second write process instead of the first write process, and transmits, to a request source of the received read request, new data stored in the cache area in the performed second write process. 2. The information processing system according to claim 1 , wherein when receiving the write request of the new data and performing the first write process, the processor ensures storage areas for storing the new data, the old data, the old parity, and the new parity in the memory, and receives the new data after ensuring the storage areas. 3. The information processing system according to claim 1 , wherein the processor further stores the new parity in the buffer area in the first write process. 4. The information processing system according to claim 1 , wherein in the first write process, the processor further stores the new data and the new parity in the storage device and deletes the old data and the old parity stored in the buffer area from the buffer area. 5. The information processing system according to claim 1 , wherein the processor stores the new data and the new parity in the cache area in second write process. 6. The information processing system according to claim 1 , wherein when storing the new data in the cache area in the second write process, the processor transmits a response to a request source of the write request, and generates the new parity after transmitting the response. 7. The information processing system according to claim 1 , wherein when storing the new data in the cache area in the second write process, the processor a response transmits to a request source of the write request, and generates the new parity asynchronously with transmitting the response. 8. The information processing system according to claim 1 , wherein the storage device includes a first storage device in which data is stored and a second storage device in which a parity is stored, the first storage device reads the old data and stores the new data, and the second storage device reads the old parity and stores the new parity. 9. An information processing method for an information processing system including a processor and a memory in which data input/output are performed with respect to a storage device, wherein the memory includes a buffer area and a cache area, the information processing method includes storing new data associated with a received write request in the memory, reading old data updated by the new data and an old parity according to the old data from the storage device, storing the old data and the old parity in the memory, generating, based on the new data, the old data, and the old parity, a new parity according to the new data, storing the new parity in the memory, storing the new data and the new parity in the storage device, wherein the information processing method further includes a first write process where the new data is to be stored in the buffer area or a second write process where the new data is to be stored in the cache area, and when receiving a read request of the new data while the first write process is in progress, performing the second write process instead of the first write process, and transmitting, to a request source of the received read request, new data stored in the cache area in the performed second write process.

Assignees

Inventors

Classifications

  • with dedicated cache, e.g. instruction or stack · CPC title

  • Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

  • being part of a memory device, e.g. cache DRAM · CPC title

  • Allocation or management of cache space · CPC title

  • Reliability improvement, data loss prevention, degraded operation etc · CPC title

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What does patent US10853268B2 cover?
An information processing system including a processor, a memory, and a plurality of drives, wherein when a write request of new data is received, the processor stores the new data in the memory, transmits a response for the write request to a transmission source of the write request, reads old data updated by the new data from a first drive of the plurality of drives and old parity related to …
Who is the assignee on this patent?
Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification G06F12/126. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).